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Date:   Fri, 16 Feb 2018 16:50:49 +0100
From:   Maxime Ripard <maxime.ripard@bootlin.com>
To:     Giulio Benetti <giulio.benetti@micronovasrl.com>
Cc:     airlied@linux.ie, wens@csie.org, dri-devel@lists.freedesktop.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] drm/sun4i: Handle DRM_MODE_FLAG_**SYNC_POSITIVE
 correctly
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On Thu, Feb 15, 2018 at 07:05:56PM +0100, Giulio Benetti wrote:
> > If so, and if remember the captures properly, the sampling would occur
> > right before the rise, and not really around the fall.
> >=20
> > Would 2/3 be better here?
>=20
> Yes, you're right, 2/3 phase is better:
>=20
> 1/3 phase: https://pasteboard.co/H4VehON.png
> 2/3 phase: https://pasteboard.co/H4Veq8a.png
>=20
> Take a look at the bit in middle(yellow) sampled by clock(blue).
>=20
> Rising edge is almost in the middle of D0 bit.
>=20
> >=20
> > > According to scope captures above on both A20 and A33.
> > > Unfortunately I don't have other boards for the other SoCs to take ca=
ptures.
> > >=20
> > > What do you think?
> >=20
> > I guess we can make that part applicable to all SoCs, we haven't seen
> > any significant differences on those part.
>=20
> So let's keep:
> - As normal(rising edge) =3D> IO_POL_REG "0x2 =3D> 2/3 phase"
> - As inverted(falling edge) =3D> IO_POL_REG "0x0 =3D> normal phase"

I was actually thinking 1/3 for rising, 2/3 for falling.

Maxime

--=20
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com

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