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The accesses are to the AMD Core Performance > Extension counters which provide 2 extra counters and new MSRs for both > the event select and counter registers. > > Since the new event select and counter MSRs are interleaved and K7 MSRs > are contiguous, the logic to map them to the gp_counters[] is changed. > > This patchset has been tested with Family 17h and Opteron G1 guests. > > v1->v2: > * Rearranged MSR #defines based on Boris's suggestion. > > v2->v3: > * Changed the logic of mapping MSR to gp_counters[] index based on > Boris's feedback. > * Removed use of family checks based on Radim's feedback. > * Removed KVM bugfix patch since it is already applied. > > v3->v4: > * Rebased to latest KVM tree. > > v4->v5: > * Removed conditional check when exposing Perf Extension flag to > guests based on Radim's feedback. > > Janakarajan Natarajan (3): > x86/msr: Add AMD Core Perf Extension MSRs > x86/kvm: Add support for AMD Core Perf Extension in guest > x86/kvm: Expose AMD Core Perf Extension flag to guests Are there any concerns regarding this patchset? Thanks. > > arch/x86/include/asm/msr-index.h | 14 ++++ > arch/x86/kvm/cpuid.c | 2 +- > arch/x86/kvm/pmu_amd.c | 140 +++++++++++++++++++++++++++++++++++---- > arch/x86/kvm/x86.c | 1 + > 4 files changed, 142 insertions(+), 15 deletions(-) >