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[209.132.180.67]) by mx.google.com with ESMTP id x6si7880967pgc.357.2018.02.18.06.53.00; Sun, 18 Feb 2018 06:53:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=WClKUHC1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751659AbeBROpM (ORCPT + 99 others); Sun, 18 Feb 2018 09:45:12 -0500 Received: from mail-qt0-f182.google.com ([209.85.216.182]:36386 "EHLO mail-qt0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751623AbeBROpK (ORCPT ); Sun, 18 Feb 2018 09:45:10 -0500 Received: by mail-qt0-f182.google.com with SMTP id q18so9401337qtl.3; Sun, 18 Feb 2018 06:45:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=pEqyTTkNnGgYP1Qdp5Q5jkwPz0gq73AfR3B4zhIl9i0=; b=WClKUHC1xayjBXELppbI4b0Go2Mqc/v5uuSEEAMyHTgmwnhI1SjdHyUjHtNkrJge8q DJj6nC1ROcwh/nnS3oYdfhEWiiwB6Hrxa/vwcey9yByaVTPB2EVXW0/Dyx/s3uoa9228 nX8eiexIZ6PTabrsk529e+yKyE6sMX5+DpAkY6Ccf2UnceQ19g4cuGCGBrh5PKhPJy9r y0C8Qg+1aKMjWkNuo0iXLLE4dr7FbYpXLjklWg+jbpZFrf6OZmachXrbLpT8EraiAYuB X3OI/CF1F+7e/uJbUktZYwYpQHRePBSLoGwfeuRrnp+TKm22wTR7+NmAURekttud1yBc gfMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=pEqyTTkNnGgYP1Qdp5Q5jkwPz0gq73AfR3B4zhIl9i0=; b=i00vxLWYHkMzEsYUPGxY0aeIrg4ronXpf1V8lo2ykpZ3ZK/sizNvWB+p9DSPlmSAmu PvgYV8I4SmTk3oP7sxoJONoO2Ydk+LIvyeoa0p/qL/3PG0B9/IOaMdw6AhoQAxGcJSLl zU5FkLbr7QBMT46mjWPj4HRqP9gc46jIe56wHs9FoKt/R2iWBzjW7BIAO7HdLqPVL2Gx SIIXwqdydIex9kWWPtmuIpU5BU5gbWX4lntC87DfoIObpQyptapJLO+uaZESIvtn3wV0 lzV7DV8xdYQOloOx+AVDVpq9FdZkK8EFEWl7hfXjuPP/jkeQ0ypNuJOif5U9H1a9uG5t /DZA== X-Gm-Message-State: APf1xPDXa1jitSi4ZHKksdiVFuY3G11HIdzgpgrBMTE5Hz+xaEAtF8Ul XHJfPli8RSvpqY1DTqSBPDMf5VViHxOihc7smjU= X-Received: by 10.200.26.79 with SMTP id q15mr19210140qtk.174.1518965109892; Sun, 18 Feb 2018 06:45:09 -0800 (PST) MIME-Version: 1.0 Received: by 10.12.195.80 with HTTP; Sun, 18 Feb 2018 06:45:09 -0800 (PST) In-Reply-To: <20180217204433.3095-9-manivannan.sadhasivam@linaro.org> References: <20180217204433.3095-1-manivannan.sadhasivam@linaro.org> <20180217204433.3095-9-manivannan.sadhasivam@linaro.org> From: Andy Shevchenko Date: Sun, 18 Feb 2018 16:45:09 +0200 Message-ID: Subject: Re: [PATCH 08/10] gpio: Add gpio driver for Actions OWL S900 SoC To: Manivannan Sadhasivam Cc: Linus Walleij , Rob Herring , =?UTF-8?Q?Andreas_F=C3=A4rber?= , =?UTF-8?B?5YiY54Kc?= , mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree , Daniel Thompson , amit.kucheria@linaro.org, linux-arm Mailing List , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Feb 17, 2018 at 10:44 PM, Manivannan Sadhasivam wrote: > Add gpio driver for Actions Semi OWL family S900 SoC. Set of registers > controlling the gpio shares the same register range with pinctrl block. > > GPIO registers are organized as 6 banks and each bank controls the > maximum of 32 gpios. > +#include > +#include Choose one of them. > + val = readl(gpio_base + GPIO_OUTEN); > + val |= BIT(offset); > + writel(val, gpio_base + GPIO_OUTEN); out_en() > + val = readl(gpio_base + GPIO_OUTEN); > + val &= ~BIT(offset); > + writel(val, gpio_base + GPIO_OUTEN); out_dis() > + val = readl(gpio_base + GPIO_INEN); > + val &= ~BIT(offset); > + writel(val, gpio_base + GPIO_INEN); in_dis() > + val = readl(gpio_base + GPIO_OUTEN); > + val &= ~BIT(offset); > + writel(val, gpio_base + GPIO_OUTEN); out_dis() > + val = readl(gpio_base + GPIO_INEN); > + val |= BIT(offset); > + writel(val, gpio_base + GPIO_INEN); in_en() > + val = readl(gpio_base + GPIO_INEN); > + val &= ~BIT(pin); > + writel(val, gpio_base + GPIO_INEN); in_dis() > + val = readl(gpio_base + GPIO_OUTEN); > + val |= BIT(pin); > + writel(val, gpio_base + GPIO_OUTEN); out_en() Find above code duplication. > +static int owl_gpio_probe(struct platform_device *pdev) > +{ > + gpio->base = of_iomap(pdev->dev.of_node, 0); > + if (IS_ERR(gpio->base)) > + return PTR_ERR(gpio->base); > + gpio->gpio.of_node = pdev->dev.of_node; Isn't this done by GPIO library? > +static int owl_gpio_remove(struct platform_device *pdev) > +{ > + return 0; > +} Useless stub. -- With Best Regards, Andy Shevchenko