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[46.139.12.213]) by smtp.gmail.com with ESMTPSA id m191sm18596552wma.42.2018.02.19.01.39.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2018 01:39:29 -0800 (PST) Date: Mon, 19 Feb 2018 10:39:27 +0100 From: Ingo Molnar To: David Woodhouse Cc: Peter Zijlstra , Tim Chen , hpa@zytor.com, tglx@linutronix.de, torvalds@linux-foundation.org, linux-kernel@vger.kernel.org, linux-tip-commits@vger.kernel.org, Borislav Petkov Subject: Re: [tip:x86/pti] x86/speculation: Use IBRS if available before calling into firmware Message-ID: <20180219093927.644jb6h5peworj62@gmail.com> References: <1518362359-1005-1-git-send-email-dwmw@amazon.co.uk> <1518808600.7876.49.camel@infradead.org> <66f94cb1-8160-56e0-680c-2e847ae05893@linux.intel.com> <20180217102616.vcwatxsgj2vunlew@gmail.com> <20180219092017.GN25201@hirez.programming.kicks-ass.net> <1519032552.7876.55.camel@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1519032552.7876.55.camel@infradead.org> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * David Woodhouse wrote: > On Mon, 2018-02-19 at 10:20 +0100, Peter Zijlstra wrote: > > > > I did not update or otherwise change packages while I was bisecting; the > > machine is: > > > > vendor_id?????? : GenuineIntel > > cpu family????? : 6 > > model?????????? : 62 > > model name????? : Intel(R) Xeon(R) CPU E5-2680 v2 @ 2.80GHz > > stepping??????? : 4 > > microcode?????? : 0x428 > > That's IVX with a microcode that doesn't *have* IBRS/IBPB. I don't > think there's a publicly available microcode that does; I assume you > didn't have one and build it into your kernel for early loading, and > thus you really weren't even using IBRS here? The code never even gets > patched in? Note that PeterZ's boot troubles only match the *symptoms* of the spurious failures reported by Tim Chen. Your commit wasn't bisected to. I linked these two reports on the (remote) possibility that they might be related via some alignment dependent bug somewhere else in the x86 kernel - possibly completely unrelated to any IBRS/IBPB details. Thanks, Ingo