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[209.132.180.67]) by mx.google.com with ESMTP id w23si5236063pgv.29.2018.02.19.05.03.56; Mon, 19 Feb 2018 05:04:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=pRAsUInh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752826AbeBSNCo (ORCPT + 99 others); Mon, 19 Feb 2018 08:02:44 -0500 Received: from smtp-fw-6001.amazon.com ([52.95.48.154]:23263 "EHLO smtp-fw-6001.amazon.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752638AbeBSNCn (ORCPT ); Mon, 19 Feb 2018 08:02:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.co.uk; i=@amazon.co.uk; q=dns/txt; s=amazon201209; t=1519045363; x=1550581363; h=from:to:subject:date:message-id; bh=8vTwu4NP5mwNc4jyA3isMErcFMnukf+oWz+3RiHaplY=; b=pRAsUInh27gqbT84YEbTTEAcoPw6DNvK32rwZMlqy81ibp2qDUtjz+9d Xmqcz6daFzXQaD7MkcLwXRyFt+tkRn3862GD7Dt1umkLVYgMlXcyrsMl0 XdEnmqjtWc/vjRbhuYmAMPTJUNK+MnPLTE/wrlbsKZzsrsXBh9M67xDxU Q=; X-IronPort-AV: E=Sophos;i="5.46,535,1511827200"; d="scan'208";a="332538163" Received: from iad6-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-1d-98acfc19.us-east-1.amazon.com) ([10.124.125.6]) by smtp-border-fw-out-6001.iad6.amazon.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 19 Feb 2018 13:02:41 +0000 Received: from uc8d3ff76b9bc5848a9cc.ant.amazon.com (iad1-ws-svc-lb91-vlan3.amazon.com [10.0.103.150]) by email-inbound-relay-1d-98acfc19.us-east-1.amazon.com (8.14.7/8.14.7) with ESMTP id w1JD2bo5058454 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 19 Feb 2018 13:02:39 GMT Received: from uc8d3ff76b9bc5848a9cc.ant.amazon.com (localhost [127.0.0.1]) by uc8d3ff76b9bc5848a9cc.ant.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id w1JD2a38022542; Mon, 19 Feb 2018 13:02:36 GMT Received: (from dwmw@localhost) by uc8d3ff76b9bc5848a9cc.ant.amazon.com (8.15.2/8.15.2/Submit) id w1JD2aPU022539; Mon, 19 Feb 2018 13:02:36 GMT From: David Woodhouse To: chris@zankel.net, jcmvbkbc@gmail.com, linux-xtensa@linux-xtensa.org, bhelgaas@google.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH] xtensa: Use generic pci_mmap_resource_range() Date: Mon, 19 Feb 2018 13:02:33 +0000 Message-Id: <1519045353-22496-1-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit f719582435 ("PCI: Add pci_mmap_resource_range() and use it for ARM64") added this generic function with the intent of using it everywhere and ultimately killing the old arch-specific implementations. Let's get on with that eradication... Signed-off-by: David Woodhouse --- arch/xtensa/include/asm/pci.h | 7 ++-- arch/xtensa/kernel/pci.c | 94 ++++--------------------------------------- 2 files changed, 12 insertions(+), 89 deletions(-) diff --git a/arch/xtensa/include/asm/pci.h b/arch/xtensa/include/asm/pci.h index 5c83798..d5a8215 100644 --- a/arch/xtensa/include/asm/pci.h +++ b/arch/xtensa/include/asm/pci.h @@ -44,9 +44,10 @@ extern struct pci_controller* pcibios_alloc_controller(void); #define PCI_DMA_BUS_IS_PHYS (1) -/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */ -#define HAVE_PCI_MMAP 1 -#define arch_can_pci_mmap_io() 1 +/* Tell PCI code what kind of PCI resource mappings we support */ +#define HAVE_PCI_MMAP 1 +#define ARCH_GENERIC_PCI_MMAP_RESOURCE 1 +#define arch_can_pci_mmap_io() 1 #endif /* __KERNEL__ */ diff --git a/arch/xtensa/kernel/pci.c b/arch/xtensa/kernel/pci.c index d981f01..b7c7a60 100644 --- a/arch/xtensa/kernel/pci.c +++ b/arch/xtensa/kernel/pci.c @@ -39,7 +39,6 @@ * pcibios_align_resource * pcibios_fixup_bus * pci_bus_add_device - * pci_mmap_page_range */ struct pci_controller* pci_ctrl_head; @@ -258,98 +257,21 @@ pci_controller_num(struct pci_dev *dev) #endif /* CONFIG_PROC_FS */ /* - * Platform support for /proc/bus/pci/X/Y mmap()s, - * modelled on the sparc64 implementation by Dave Miller. + * Platform support for /proc/bus/pci/X/Y mmap()s. * -- paulus. */ -/* - * Adjust vm_pgoff of VMA such that it is the physical page offset - * corresponding to the 32-bit pci bus offset for DEV requested by the user. - * - * Basically, the user finds the base address for his device which he wishes - * to mmap. They read the 32-bit value from the config space base register, - * add whatever PAGE_SIZE multiple offset they wish, and feed this into the - * offset parameter of mmap on /proc/bus/pci/XXX for that device. - * - * Returns negative error code on failure, zero on success. - */ -static __inline__ int -__pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma, - enum pci_mmap_state mmap_state) +int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma) { - struct pci_controller *pci_ctrl = (struct pci_controller*) dev->sysdata; - unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; - unsigned long io_offset = 0; - int i, res_bit; + struct pci_controller *pci_ctrl = (struct pci_controller*) pdev->sysdata; + resource_size_t ioaddr = pci_resource_start(pdev, bar); if (pci_ctrl == 0) return -EINVAL; /* should never happen */ - /* If memory, add on the PCI bridge address offset */ - if (mmap_state == pci_mmap_mem) { - res_bit = IORESOURCE_MEM; - } else { - io_offset = (unsigned long)pci_ctrl->io_space.base; - offset += io_offset; - res_bit = IORESOURCE_IO; - } - - /* - * Check that the offset requested corresponds to one of the - * resources of the device. - */ - for (i = 0; i <= PCI_ROM_RESOURCE; i++) { - struct resource *rp = &dev->resource[i]; - int flags = rp->flags; - - /* treat ROM as memory (should be already) */ - if (i == PCI_ROM_RESOURCE) - flags |= IORESOURCE_MEM; - - /* Active and same type? */ - if ((flags & res_bit) == 0) - continue; - - /* In the range of this resource? */ - if (offset < (rp->start & PAGE_MASK) || offset > rp->end) - continue; - - /* found it! construct the final physical address */ - if (mmap_state == pci_mmap_io) - offset += pci_ctrl->io_space.start - io_offset; - vma->vm_pgoff = offset >> PAGE_SHIFT; - return 0; - } - - return -EINVAL; -} + /* Convert to an offset within this PCI controller */ + ioaddr -= (unsigned long)pci_ctrl->io_space.base; -/* - * Perform the actual remap of the pages for a PCI device mapping, as - * appropriate for this architecture. The region in the process to map - * is described by vm_start and vm_end members of VMA, the base physical - * address is found in vm_pgoff. - * The pci device structure is provided so that architectures may make mapping - * decisions on a per-device or per-bus basis. - * - * Returns a negative error code on failure, zero on success. - */ -int pci_mmap_page_range(struct pci_dev *dev, int bar, - struct vm_area_struct *vma, - enum pci_mmap_state mmap_state, - int write_combine) -{ - int ret; - - ret = __pci_mmap_make_offset(dev, vma, mmap_state); - if (ret < 0) - return ret; - - vma->vm_page_prot = pgprot_device(vma->vm_page_prot); - - ret = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, - vma->vm_end - vma->vm_start,vma->vm_page_prot); - - return ret; + vma->vm_pgoff += (ioaddr + pci_ctrl->io_space.start) >> PAGE_SHIFT; + return 0; } -- 2.7.4