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[209.85.128.173]) by smtp.gmail.com with ESMTPSA id l5sm11172350eda.82.2018.02.19.19.17.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 19 Feb 2018 19:17:27 -0800 (PST) Received: by mail-wr0-f173.google.com with SMTP id n7so11613231wrn.5; Mon, 19 Feb 2018 19:17:27 -0800 (PST) X-Received: by 10.223.186.197 with SMTP id w5mr16138831wrg.155.1519096647152; Mon, 19 Feb 2018 19:17:27 -0800 (PST) MIME-Version: 1.0 Received: by 10.223.134.148 with HTTP; Mon, 19 Feb 2018 19:17:06 -0800 (PST) In-Reply-To: <694c5137-0020-bb62-68c7-f9729c101462@gmail.com> References: <20180217130504.8668-1-wens@csie.org> <694c5137-0020-bb62-68c7-f9729c101462@gmail.com> From: Chen-Yu Tsai Date: Tue, 20 Feb 2018 11:17:06 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] clk: sunxi-ng: a31: Fix CLK_OUT_* clock ops To: Philipp Rossak Cc: Maxime Ripard , Michael Turquette , Stephen Boyd , linux-clk , linux-arm-kernel , linux-kernel , stable Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Feb 17, 2018 at 9:54 PM, Philipp Rossak wrote: > > > On 17.02.2018 14:05, Chen-Yu Tsai wrote: >> >> When support for the A31/A31s CCU was first added, the clock ops for >> the CLK_OUT_* clocks was set to the wrong type. The clocks are MP-type, >> but the ops was set for div (M) clocks. This went unnoticed until now. >> This was because while they are different clocks, their data structures >> aligned in a way that ccu_div_ops would access the second ccu_div_internal >> and ccu_mux_internal structures, which were valid, if not incorrect. >> >> Furthermore, the use of these CLK_OUT_* was for feeding a precise 32.768 >> kHz clock signal to the WiFi chip. This was achievable by using the parent >> with the same clock rate and no divider. So the incorrect divider setting >> did not affect this usage. >> >> Commit 946797aa3f08 ("clk: sunxi-ng: Support fixed post-dividers on MP >> style clocks") added a new field to the ccu_mp structure, which broke >> the aforementioned alignment. Now the system crashes as div_ops tries >> to look up a nonexistent table. >> >> Reported-by: Philipp Rossak >> Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks") >> Cc: >> Signed-off-by: Chen-Yu Tsai > > Tested-by: Philipp Rossak >> >> --- >> >> Philipp, can you give this a test and report if this fixes thing? >> I don't have any A31/A31s boards online to test this. >> > Thanks! > That fixes that bug! Thanks. It looks like this has been applied by Maxime.