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[209.132.180.67]) by mx.google.com with ESMTP id p33-v6si1117519pld.310.2018.02.20.01.25.43; Tue, 20 Feb 2018 01:26:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=ehdk4SZ/; dkim=pass header.i=@codeaurora.org header.s=default header.b=fZUA1bj6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751260AbeBTJZC (ORCPT + 99 others); Tue, 20 Feb 2018 04:25:02 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:46404 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751012AbeBTJY7 (ORCPT ); Tue, 20 Feb 2018 04:24:59 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D2F41602BA; Tue, 20 Feb 2018 09:24:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1519118698; bh=1cGrl7lLoDBQsh/EdCZ+/gFA20Kyx/VUcqeHDy85oKo=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=ehdk4SZ/mdhj0RpjzTG7t6KJ6sKyRG/NOga13HqdCKGyXaLRah25/6OA4as7KBIa4 kW6h/DSm/sazyNL4lzP8u70EH2worqxmXh0SxnemdnWJ1XZwAWAApvk/0PuYPcbSjs IMoZlQVzJSiRhIfSjJXenh/gIQ5fQ8os5cjuwDSM= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from [10.204.100.248] (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: cpandya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2323A602BA; Tue, 20 Feb 2018 09:24:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1519118685; bh=1cGrl7lLoDBQsh/EdCZ+/gFA20Kyx/VUcqeHDy85oKo=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=fZUA1bj6QNsa/yULD5ZHC2kyoGXpZMpMUkVTQ3gHVy4WA8QRneoSZw7L8DB7lcYuv Be7c1kzdIASXlkxoLIsk0k0bYQmUY+dIUMoTee2PQret06fFGHgx4an8X5AgEdOUDC +dZnrNiZLPB1goKyfsiTKqUpueCUQI2Tf9Ev2An0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2323A602BA Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=cpandya@codeaurora.org Subject: Re: [RFC patch] ioremap: don't set up huge I/O mappings when p4d/pud/pmd is zero To: Hanjun Guo , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Mark Rutland , Michal Hocko , Toshi Kani , Xuefeng Wang , Catalin Marinas , Will Deacon , linuxarm@huawei.com, linux-mm@kvack.org, Hanjun Guo , Andrew Morton References: <1514460261-65222-1-git-send-email-guohanjun@huawei.com> From: Chintan Pandya Message-ID: <861128ce-966f-7006-45ba-6a7298918686@codeaurora.org> Date: Tue, 20 Feb 2018 14:54:39 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <1514460261-65222-1-git-send-email-guohanjun@huawei.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/28/2017 4:54 PM, Hanjun Guo wrote: > From: Hanjun Guo > > When we using iounmap() to free the 4K mapping, it just clear the PTEs > but leave P4D/PUD/PMD unchanged, also will not free the memory of page > tables. > > This will cause issues on ARM64 platform (not sure if other archs have > the same issue) for this case: > > 1. ioremap a 4K size, valid page table will build, > 2. iounmap it, pte0 will set to 0; > 3. ioremap the same address with 2M size, pgd/pmd is unchanged, > then set the a new value for pmd; > 4. pte0 is leaked; > 5. CPU may meet exception because the old pmd is still in TLB, > which will lead to kernel panic. > > Fix it by skip setting up the huge I/O mappings when p4d/pud/pmd is > zero. > One obvious problem I see here is, once any 2nd level entry has 3rd level mapping, this entry can't map 2M section ever in future. This way, we will fragment entire virtual space over time. The code you are changing is common between 32-bit systems as well (I think). And running out of section mapping would be a reality in practical terms. So, if we can do the following as a fix up, we would be saved. 1) Invalidate 2nd level entry from TLB, and 2) Free the page which holds last level page table BTW, is there any further discussion going on this topic which I am missing ? > Reported-by: Lei Li > Signed-off-by: Hanjun Guo > Cc: Toshi Kani > Cc: Mark Rutland > Cc: Will Deacon > Cc: Catalin Marinas > Cc: Michal Hocko > Cc: Andrew Morton > Cc: Xuefeng Wang > --- > > Not sure if this is the right direction, this patch has a obvious > side effect that a mapped address with 4K will not back to 2M. I may > miss something and just wrong, so this is just a RFC version, comments > are welcomed. > > lib/ioremap.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/lib/ioremap.c b/lib/ioremap.c > index b808a39..4e6f19a 100644 > --- a/lib/ioremap.c > +++ b/lib/ioremap.c > @@ -89,7 +89,7 @@ static inline int ioremap_pmd_range(pud_t *pud, unsigned long addr, > do { > next = pmd_addr_end(addr, end); > > - if (ioremap_pmd_enabled() && > + if (ioremap_pmd_enabled() && pmd_none(*pmd) && > ((next - addr) == PMD_SIZE) && > IS_ALIGNED(phys_addr + addr, PMD_SIZE)) { > if (pmd_set_huge(pmd, phys_addr + addr, prot)) > @@ -115,7 +115,7 @@ static inline int ioremap_pud_range(p4d_t *p4d, unsigned long addr, > do { > next = pud_addr_end(addr, end); > > - if (ioremap_pud_enabled() && > + if (ioremap_pud_enabled() && pud_none(*pud) && > ((next - addr) == PUD_SIZE) && > IS_ALIGNED(phys_addr + addr, PUD_SIZE)) { > if (pud_set_huge(pud, phys_addr + addr, prot)) > @@ -141,7 +141,7 @@ static inline int ioremap_p4d_range(pgd_t *pgd, unsigned long addr, > do { > next = p4d_addr_end(addr, end); > > - if (ioremap_p4d_enabled() && > + if (ioremap_p4d_enabled() && p4d_none(*p4d) && > ((next - addr) == P4D_SIZE) && > IS_ALIGNED(phys_addr + addr, P4D_SIZE)) { > if (p4d_set_huge(p4d, phys_addr + addr, prot)) > Chintan -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project