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[209.132.180.67]) by mx.google.com with ESMTP id i6si1088589pgq.471.2018.02.20.04.57.48; Tue, 20 Feb 2018 04:58:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=vEa4zSJ3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751839AbeBTM4h (ORCPT + 99 others); Tue, 20 Feb 2018 07:56:37 -0500 Received: from mail-qk0-f193.google.com ([209.85.220.193]:35807 "EHLO mail-qk0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751629AbeBTM4f (ORCPT ); Tue, 20 Feb 2018 07:56:35 -0500 Received: by mail-qk0-f193.google.com with SMTP id s188so6540406qkb.2; Tue, 20 Feb 2018 04:56:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=BDFB+YwKUAZLw4VoAHte9K/d6+i1mDYSvbV5X88Gp1U=; b=vEa4zSJ3lMuLOZXVtccRmJ/TJV9PNlaN+IBwEpQqyL46ZX1K9y40AGd3oKd1laoIck cfHLw+87EngS26cSkz3juDFGXbmHthoyiahCe34yPsVr6Mi7eyy4h/xqCWu6CayA2j8w IT8MV1DcXkr60X5d2yLe+SsfxkAdHnt4o4aDtkJrfu+9bOsGXrwuC2rmgT1TT8br1rLb dDzyABVW06XROTeWvlicdm0p954jBqJzdh5LYW1t4+kj4JR8uiyseyI7X2E+VZdbgMJV ssJphf0LT5JqiGx8lDXp9pi8j+SorL2K5ketgaKkiCzxU15v9UDBY6ugGYw4jdQuoOJF SwZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=BDFB+YwKUAZLw4VoAHte9K/d6+i1mDYSvbV5X88Gp1U=; b=QBCF/yRfpHqBIJWkP8LoR5y+F6kDwjl9877VlNz/L1BKQn5g9St6qNn/xUJycgGUlH w7pN0w6Q9r3QYe5KbsKQpmSIMm2rUoc/i+2jDV4xAcQNxmreM7vIBL8vOWTOC9Q877rn 9h1GghmPZZjwYQNwl+H2Y5QVZrofLeUA7FrRF3OeMe1R9Q0A8aVlOQnR7Y9TQwRIPyAI zo41g/xPW949ez0r5JPUYqhIhYfmTBdf+vk0s8UNPZV1rtbwkwVXwdFdSAtUdJdXaXEn 58N5db46kzLAyOJ2XG8WWgGoZofj5KDqovYGTPDULloG1Ga9w6GX0gVmhzuXeLIoqM+D rR9Q== X-Gm-Message-State: APf1xPDIyxVbLpuaSB5ft/I7I/UFym4Wqzu8N711BrXd2OsZpcTTDOJo CR+/HHKtGEFh8jNiy0EAw5e0Td46shDE1meFqZU= X-Received: by 10.55.245.9 with SMTP id l9mr29936901qkk.301.1519131394796; Tue, 20 Feb 2018 04:56:34 -0800 (PST) MIME-Version: 1.0 Received: by 10.12.195.80 with HTTP; Tue, 20 Feb 2018 04:56:33 -0800 (PST) In-Reply-To: <1519077427-30165-1-git-send-email-david@lechnology.com> References: <1519077427-30165-1-git-send-email-david@lechnology.com> From: Andy Shevchenko Date: Tue, 20 Feb 2018 14:56:33 +0200 Message-ID: Subject: Re: [PATCH v2] pinctrl: pinctrl-single: Fix pcs_request_gpio() when bits_per_mux != 0 To: David Lechner Cc: linux-arm Mailing List , Linux OMAP Mailing List , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Tony Lindgren , Haojian Zhuang , Linus Walleij Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Feb 19, 2018 at 11:57 PM, David Lechner wrote: > This fixes pcs_request_gpio() in the pinctrl-single driver when > bits_per_mux != 0. It appears this was overlooked when the multiple > pins per register feature was added. > > Fixes: 4e7e8017a80e ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules") > Signed-off-by: David Lechner > --- > > v2 changes: > - don't wrap Fixes: line in commit message since it is a special machine- > readable line. > > There was some discussion in v1 about using DIV_ROUND_UP(), etc. macros, but > the consensus was to leave it as-is since it matches existing code and that > macros can be introduced in another patch. > > drivers/pinctrl/pinctrl-single.c | 22 +++++++++++++++++++--- > 1 file changed, 19 insertions(+), 3 deletions(-) > > diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c > index cec7537..a7c5eb3 100644 > --- a/drivers/pinctrl/pinctrl-single.c > +++ b/drivers/pinctrl/pinctrl-single.c > @@ -391,9 +391,25 @@ static int pcs_request_gpio(struct pinctrl_dev *pctldev, > || pin < frange->offset) > continue; > mux_bytes = pcs->width / BITS_PER_BYTE; > - data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask; > - data |= frange->gpiofunc; > - pcs->write(data, pcs->base + pin * mux_bytes); > + > + if (pcs->bits_per_mux) { > + int byte_num, offset, pin_shift; > + > + byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE; > + offset = (byte_num / mux_bytes) * mux_bytes; > + pin_shift = pin % (pcs->width / pcs->bits_per_pin) * > + pcs->bits_per_pin; > + > + data = pcs->read(pcs->base + offset); > + data &= ~(pcs->fmask << pin_shift); > + data |= frange->gpiofunc << pin_shift; > + pcs->write(data, pcs->base + offset); > + } else { > + data = pcs->read(pcs->base + pin * mux_bytes); > + data &= ~pcs->fmask; > + data |= frange->gpiofunc; > + pcs->write(data, pcs->base + pin * mux_bytes); Just an idea, you may leave this almost untouched and do calculate pin_shift and offset in condition, like if (...) { pin_shift = ... offset = ... } else { pin_shift = 0; offset = pin * mux_bytes; } data = pcs->read(pcs->base + offset); data &= ~(pcs->fmask << pin_shift); data |= frange->gpiofunc << pin_shift; pcs->write(data, pcs->base + offset); It's also possible to split to two changes, where first introduces that variables and their default values (see 'else' branch) and second one introduces an if branch override. > + } > break; -- With Best Regards, Andy Shevchenko