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[209.132.180.67]) by mx.google.com with ESMTP id t10-v6si1683plq.569.2018.02.20.06.34.30; Tue, 20 Feb 2018 06:34:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=myml/Kn6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751368AbeBTOdt (ORCPT + 99 others); Tue, 20 Feb 2018 09:33:49 -0500 Received: from mail-qk0-f195.google.com ([209.85.220.195]:33522 "EHLO mail-qk0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750988AbeBTOdq (ORCPT ); Tue, 20 Feb 2018 09:33:46 -0500 Received: by mail-qk0-f195.google.com with SMTP id f25so16660003qkm.0; Tue, 20 Feb 2018 06:33:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=0sNc3xLOP6zoQzlSH0dO9C/2yR9TH2SIp2faZRny6ig=; b=myml/Kn6tbOC2hYIfQs/KYjEG2zYtiJKrNqZlJcLu/dLLh1onulc3KsFybzKdHCcrT ykZJnnBCxKeHlYwconEu96Mji4eef8rWZoJmLMBR0twgPWgn3tV7NU8UPkUkpqzZPjpf gf5K5LR390d9QvB0odIiC5CzydMQwb8h3hoVr9stc5mThSwiDpHz98K4vvs7F5lA2qdA hsjpE54bCSN8L008bryTv7FvN23qiqLRSegjyAr3pBfwWhkaa/paDjCC8Iqak3IR/UPJ hkm1mbzUCCc9G922WsBEy+gzPSc0FyC/WuFUZFLyUECeD5GRaR64ipkV6uoqcoiprD8L fxUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=0sNc3xLOP6zoQzlSH0dO9C/2yR9TH2SIp2faZRny6ig=; b=FugkUrZqxFzpxY3PdjnfpYTu+LoE33nfxgW1a0CbW8wqVB1ZVo+E6z6yDOT3P9frSl zFrL8EfMpUg3qwDdpVzYTJp3rLWgPoyqiBOJibmsdDzmBI1RAhl5OBA4KKr0SjrFE3Iv hKgzEpwsjxhV5DdgZiPlJIiqZEuzaJVMHFIMX7V8/nafJQ0Zc50Wz5FhqEI6d/TvqBr8 sGWo34WRkh5qmrcKw8oXnUqJuAVjvCwbJiHkabvedE3C8qE3K3RzlsiB3AtqfnZnpSux VV3zwbVtMlZ1sfagS57fA0Yn3TKbeq1IiSlC5blSfnN75wYPoYbZxpsRHB434dzkv17a eYpw== X-Gm-Message-State: APf1xPAW3i4TeskyLOiKPpC+/uU5inOQHuf5LYjbifFsDrIvd7O7btjj WWM4YCTVusrVS4ndON5x2mVRUgjGxfyZLmdeaVk= X-Received: by 10.55.16.196 with SMTP id 65mr30014150qkq.110.1519137225835; Tue, 20 Feb 2018 06:33:45 -0800 (PST) MIME-Version: 1.0 Received: by 10.12.195.80 with HTTP; Tue, 20 Feb 2018 06:33:45 -0800 (PST) In-Reply-To: <1519062520-198902-2-git-send-email-john.garry@huawei.com> References: <1519062520-198902-1-git-send-email-john.garry@huawei.com> <1519062520-198902-2-git-send-email-john.garry@huawei.com> From: Andy Shevchenko Date: Tue, 20 Feb 2018 16:33:45 +0200 Message-ID: Subject: Re: [PATCH v14 1/9] LIB: Introduce a generic PIO mapping method To: John Garry Cc: Mika Westerberg , "Rafael J. Wysocki" , Lorenzo Pieralisi , "Rafael J. Wysocki" , Hanjun Guo , Rob Herring , Bjorn Helgaas , Arnd Bergmann , Mark Rutland , Olof Johansson , Dann Frazier , Rob Herring , Joe Perches , Benjamin Herrenschmidt , linux-pci@vger.kernel.org, Linux Kernel Mailing List , ACPI Devel Maling List , Linuxarm , Corey Minyard , devicetree , Linux-Arch , Randy Dunlap Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Feb 19, 2018 at 7:48 PM, John Garry wrote: > From: Zhichang Yuan > > In commit 41f8bba7f555 ("of/pci: Add pci_register_io_range() and > pci_pio_to_address()"), a new I/O space management was supported. With > that driver, the I/O ranges configured for PCI/PCIe hosts on some > architectures can be mapped to logical PIO, converted easily between > CPU address and the corresponding logicial PIO. Based on this, PCI > I/O devices can be accessed in a memory read/write way through the > unified in/out accessors. > > But on some archs/platforms, there are bus hosts which access I/O > peripherals with host-local I/O port addresses rather than memory > addresses after memory-mapped. > > To support those devices, a more generic I/O mapping method is introduced > here. Through this patch, both the CPU addresses and the host-local port > can be mapped into the logical PIO space with different logical/fake PIOs. > After this, all the I/O accesses to either PCI MMIO devices or host-local > I/O peripherals can be unified into the existing I/O accessors defined in > asm-generic/io.h and be redirected to the right device-specific hooks > based on the input logical PIO. > +#define PIO_INDIRECT 0x01UL /* indirect IO flag */ > +#define PIO_CPU_MMIO 0x00UL /* memory mapped io flag */ It looks like bitfield, but from use I don't see it. Perhaps use enum instead? > + resource_size_t hwaddr = -1; > +unsigned long > + return -1; > + return -1; > +unsigned long > + return -1; > +type logic_in##bw(unsigned long addr) \ > + type ret = -1; \ All types above are unsigned. I'm not sure it's the best approach to use -1 implicitly casted to unsigned type. I would rather use ~0UL or alike. -- With Best Regards, Andy Shevchenko