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[209.132.180.67]) by mx.google.com with ESMTP id e1-v6si658768pld.586.2018.02.20.23.40.17; Tue, 20 Feb 2018 23:40:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=bNfzrtcx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751560AbeBUHVE (ORCPT + 99 others); Wed, 21 Feb 2018 02:21:04 -0500 Received: from mail-ua0-f195.google.com ([209.85.217.195]:42051 "EHLO mail-ua0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751359AbeBUHVD (ORCPT ); Wed, 21 Feb 2018 02:21:03 -0500 Received: by mail-ua0-f195.google.com with SMTP id b15so421374uaf.9 for ; Tue, 20 Feb 2018 23:21:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=vSp6ixg+B85S8YrdAXTVyvBHibicN+SflprEnG0C5FA=; b=bNfzrtcx4hfvcFuf8MJJ2cTl1809xCdzXwbtOxp57AZGKwOHfpLSWq3TV4vNFquWkt dDjSFh1ULUTs5PDWjHyMIApE7/f+UxYYY2ON3FKax1wBmDXETSVEOTGnSUA9g75ACWXR TqfKkiQatpadHvDhN5vbyWSSsIsxREB4kzy1wMmgH0VucYCg16rT1HvlxT75npCQVGWg xZ7naNdXK/ehGagQFbtC8vXtwFxL7tLJzuLe/7NmHzeTb0eTl5/v9tbVAlRxdsEfGt/F CSjeLF1bxOgkrmR2Ow6mfegDTgF1EmYVCtRaDRUQfgyKStFLK1O4YstgTfodf88YpUi0 m6Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=vSp6ixg+B85S8YrdAXTVyvBHibicN+SflprEnG0C5FA=; b=CAdYnl6SbZF5BkTusHhghc0teePbWY9ALAO1+S3SZ5Xv98Sh2mq903xv+XhX++744X P1ku2DDYat7WFLBIrm96JjbDKF+xLonhWq/+uPOAUSepoeSf3jwf6XYHT/VUha1g0jo7 etoXIWl4gULiHcBOoEMrQFM/KDy6rabdPqYeUCH6Pv3llna6uMkkhQDwl18Z3zAMIUYz xkIcbRjtfC/XzE1XE3JBOqxhmkIOPVI7gTpzNp9lwJJA7i6s6fxhRHWc/jan/WzSHFtR r1XNSTphruGd3kOylTxu964T/Pqh545eWq4epPabOIPhrQDF6xGTgFO93+vMmcmmvf/9 Ms2w== X-Gm-Message-State: APf1xPBrYXZCeC0S/SZRsp4dLS7ecqeQQ91MGaXSnND5VB0HIRgmdlOP ITsnnCNQI7eTM+vLWCR/L27zbLLIWVIiQL0Cj6k= X-Received: by 10.159.37.226 with SMTP id 89mr1801358uaf.1.1519197662262; Tue, 20 Feb 2018 23:21:02 -0800 (PST) MIME-Version: 1.0 Received: by 10.159.49.66 with HTTP; Tue, 20 Feb 2018 23:20:21 -0800 (PST) In-Reply-To: References: From: Greentime Hu Date: Wed, 21 Feb 2018 15:20:21 +0800 Message-ID: Subject: Re: [PATCH v7 0/3] clocksource/drivers/atcpit100: Add andestech atcpit100 timer To: Greentime , Linux Kernel Mailing List , Arnd Bergmann , Vincent Chen , Daniel Lezcano , Linus Walleij , Rick Chen Cc: Green Hu Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2018-02-13 17:13 GMT+08:00 Greentime Hu : > Hi, all: > > ATCPIT100 is often used on the Andes architecture, > This timer provide 4 PIT channels. Each PIT channel is a > multi-function timer, can be configured as 32,16,8 bit timers > or PWM as well. > > For system timer it will set channel 1 32-bit timer0 as clock > source and count downwards until underflow and restart again. > > It also set channel 0 32-bit timer0 as clock event and count > downwards until condition match. It will generate an interrupt > for handling periodically. > > Changes in v7: > - Fix atcpit100_clkevt_next_event(), before set reload register, > clock source timer shall disable. And re-enable it after the setting. > Without this modification, the test case 'clock_nanosleep02' of ltp_20170929 > will fail. > > Changes in v6: > - To select TIMER_OF in drivers/clocksource/Kconfig instead of arch/nds32/Kconfig > - Refine Kconfig > - Update license format to SPDX-License-Identifier > > > Rick Chen (3): > clocksource/drivers/atcpit100: Add andestech atcpit100 timer > clocksource/drivers/atcpit100: VDSO support > dt-bindings: timer: Add andestech atcpit100 timer binding doc > > .../bindings/timer/andestech,atcpit100-timer.txt | 33 +++ > drivers/clocksource/Kconfig | 9 + > drivers/clocksource/Makefile | 1 + > drivers/clocksource/timer-atcpit100.c | 266 +++++++++++++++++++++ > 4 files changed, 309 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt > create mode 100644 drivers/clocksource/timer-atcpit100.c > Hi, Daniel: Please merge this driver for 4.17 to go along with the nds32 architeture support. Thank you.