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[209.132.180.67]) by mx.google.com with ESMTP id 33-v6si2939568plk.576.2018.02.21.11.10.25; Wed, 21 Feb 2018 11:10:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=NiWJEh7J; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934790AbeBURdm (ORCPT + 99 others); Wed, 21 Feb 2018 12:33:42 -0500 Received: from mail-io0-f172.google.com ([209.85.223.172]:41721 "EHLO mail-io0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934375AbeBURdj (ORCPT ); Wed, 21 Feb 2018 12:33:39 -0500 Received: by mail-io0-f172.google.com with SMTP id e4so2944572iob.8; Wed, 21 Feb 2018 09:33:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=OoSlCj0r/Cgra4FXucNcPwaNwpTk9SRw8kI7LKydIx4=; b=NiWJEh7JgNF6K0HWqxs2iucWHKZsap3kcZxDg+Rsl3w/ZAL+g0J8E2SzGIFCi2SivM XVrO8PpuZy2UGIKQq8FiVkneq9AwrMZPW6LkvgMLx6qACM8tM50uQsWA+kXAxWu6M7ET F77o+mEE2wsPP6cCItoK5Zot6uMOKlWj+DeGqd20B/NYnXAsknQS5Xj8XBHrF4re2aZh 8ACeeyHsD2HkcJ1Hr0WdhD0ys2//RymFVgwly4tXiILyDwboR49cT3P0zX70iWmQog4h jV81+0JYuxvgIfB0oIHC/r76pC7aMb6Ujfn8Tsn/bT2ssdEHvyw8MK0c2vC/ZA8SH8qg Os9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=OoSlCj0r/Cgra4FXucNcPwaNwpTk9SRw8kI7LKydIx4=; b=REk82PkQ3BgCJKMTHRXbPhioYUtxUVYRJnfX+b7Y2GLOZUI/SABkGyIcSSQrJ2WGM8 0XO6qQvo3iTPwS1Fk3B84gfRglZa/OhYUoLgD8mbBSFRBZe4Um4j8qlBcY4mtzE3IvBu 3RaN36ay71YDKaxoB4by4jWHLTTypdo3G4SfeNKg/zf82gybprGVyQI9XKZUui4xD6SA /DWvMlqS4IExED0hpp+4oeArAxhpfEM4TB8mH5jVyKdQcgGjSZ833gZoSMDzmH/mouEL TIEWcQJ5HHWHDk1zY7S9Q3rcWBWo+cQlNMXhMS4YJBYOv+1Sa/K/diRSdMSNG5+oVppj jCwg== X-Gm-Message-State: APf1xPDElsd3Bgcg55nIfolInsVsE6netTlTLChK1Y0j7ZqKuSOf3g9q CuNbz4MaTLv1yMFcSDImQSr3V2NmzH1FM8lgiM6W5Q== X-Received: by 10.107.8.2 with SMTP id 2mr4929136ioi.167.1519234418403; Wed, 21 Feb 2018 09:33:38 -0800 (PST) MIME-Version: 1.0 Received: by 10.2.92.211 with HTTP; Wed, 21 Feb 2018 09:33:36 -0800 (PST) In-Reply-To: <20180221163654.GS5453@intel.com> References: <20180221143730.30285-1-robdclark@gmail.com> <20180221143730.30285-2-robdclark@gmail.com> <20180221144919.GN5453@intel.com> <20180221150727.GO5453@intel.com> <20180221152720.GP5453@intel.com> <20180221155410.GQ5453@intel.com> <20180221163654.GS5453@intel.com> From: Rob Clark Date: Wed, 21 Feb 2018 12:33:36 -0500 Message-ID: Subject: Re: [PATCH 1/4] drm/atomic: integrate modeset lock with private objects To: =?UTF-8?B?VmlsbGUgU3lyasOkbMOk?= Cc: dri-devel , David Airlie , linux-arm-msm , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Feb 21, 2018 at 11:36 AM, Ville Syrj=C3=A4l=C3=A4 wrote: > On Wed, Feb 21, 2018 at 11:17:21AM -0500, Rob Clark wrote: >> On Wed, Feb 21, 2018 at 10:54 AM, Ville Syrj=C3=A4l=C3=A4 >> wrote: >> > On Wed, Feb 21, 2018 at 10:36:06AM -0500, Rob Clark wrote: >> >> On Wed, Feb 21, 2018 at 10:27 AM, Ville Syrj=C3=A4l=C3=A4 >> >> wrote: >> >> > On Wed, Feb 21, 2018 at 10:20:03AM -0500, Rob Clark wrote: >> >> >> On Wed, Feb 21, 2018 at 10:07 AM, Ville Syrj=C3=A4l=C3=A4 >> >> >> wrote: >> >> >> > On Wed, Feb 21, 2018 at 09:54:49AM -0500, Rob Clark wrote: >> >> >> >> On Wed, Feb 21, 2018 at 9:49 AM, Ville Syrj=C3=A4l=C3=A4 >> >> >> >> wrote: >> >> >> >> > On Wed, Feb 21, 2018 at 09:37:21AM -0500, Rob Clark wrote: >> >> >> >> >> Follow the same pattern of locking as with other state objec= ts. This >> >> >> >> >> avoids boilerplate in the driver. >> >> >> >> > >> >> >> >> > I'm not sure we really want to do this. What if the driver wa= nts a >> >> >> >> > custom locking scheme for this state? >> >> >> >> >> >> >> >> That seems like something we want to discourage, ie. all the mo= re >> >> >> >> reason for this patch. >> >> >> >> >> >> >> >> There is no reason drivers could not split their global state i= nto >> >> >> >> multiple private objs's, each with their own lock, for more fin= e >> >> >> >> grained locking. That is basically the only valid reason I can= think >> >> >> >> of for "custom locking". >> >> >> > >> >> >> > In i915 we have at least one case that would want something clos= e to an >> >> >> > rwlock. Any crtc lock is enough for read, need all of them for w= rite. >> >> >> > Though if we wanted to use private objs for that we might need t= o >> >> >> > actually make the states refcounted as well, otherwise I can ima= gine >> >> >> > we might land in some use-after-free issues once again. >> >> >> > >> >> >> > Maybe we could duplicate the state into per-crtc and global copi= es, but >> >> >> > then we have to keep all of those in sync somehow which doesn't = sound >> >> >> > particularly pleasant. >> >> >> >> >> >> Or just keep your own driver lock for read, and use that plus the = core >> >> >> modeset lock for write? >> >> > >> >> > If we can't add the private obj to the state we can't really use it= . >> >> > >> >> >> >> I'm not sure why that is strictly true (that you need to add it to th= e >> >> state if for read-only), since you'd be guarding it with your own >> >> driver read-lock you can just priv->foo_state->bar. >> >> >> >> Since it is read-only access, there is no roll-back to worry about fo= r >> >> test-only or failed atomic_check()s.. >> > >> > That would be super ugly. We want to access the information the same >> > way whether it has been modified or not. >> >> Well, I mean the whole idea of what you want to do seems a bit super-ugl= y ;-) >> >> I mean, in mdp5 the assigned global resources go in plane/crtc state, >> and tracking of what is assigned to which plane/crtc is in global >> state, so it fits nicely in the current locking model. For i915, I'm >> not quite sure what is the global state you are concerned about, so it >> is a bit hard to talk about the best solution in the abstract. Maybe >> the better option is to teach modeset-lock how to be a rwlock instead? > > The thing I'm thinking is the core display clock (cdclk) frequency which > we need to consult whenever computing plane states and whatnot. We don't > want a modeset on one crtc to block a plane update on another crtc > unless we actually have to bump the cdclk (which would generally require > all crtcs to undergo a full modeset). Seems like a generally useful > pattern to me. > Hmm.. I suppose either way, you'd have to make modeset-lock have rw semantics or invent some way to play nicely with acquire_ctx.. once you have that, I'd have no objection to make private state use rwlock semantics. That seems better than having drivers (badly) roll their own. And maybe as you say, it would be a useful pattern for other drivers. BR, -R