Received: by 10.223.185.116 with SMTP id b49csp1052548wrg; Wed, 21 Feb 2018 11:14:35 -0800 (PST) X-Google-Smtp-Source: AH8x2243NM/kxbtWT73yO4hM75eDP5vzgr34NLR9VjBUGxccZIhURAlF6J/feXcsNjehMu3sWqwd X-Received: by 10.99.120.193 with SMTP id t184mr3592638pgc.348.1519240475334; Wed, 21 Feb 2018 11:14:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519240475; cv=none; d=google.com; s=arc-20160816; b=K3CzCGBYm2aGKHkn8XgwnHnW/LedGpmNlGx3EjX2CuJO+F9Vw62mE9JwuXgVM7UO/g xIP6P/Qw7kOlRDEiT4mYAkged76469rTLfa0MF9sgggoUpYNVKflmnLF++3eW4z8jJm8 wcveFE277/nxIPZ3jHWPdrBp9oNJ3pIWA64eT3gf4a8RrX7RJO1rblg3BRbIq4uB/2j+ yQjuGdu2WVCUqiHMMzJ+ujh8AzckrB5zSXUpNV1Pvtfv+w5ocjtwLiIgbnwl/Num5hId rEbGvIxedmJODVJ6ahU9n1fMX93JLSBFiD+Xg+fAfnsGkqisEHsJYvz8X0PzBLELHjD2 5UDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-transfer-encoding:content-disposition:mime-version :references:message-id:subject:cc:to:from:date :arc-authentication-results; bh=vEfaP6A1LptPo0q40JtZ2lCrS9NFrShKV7Jki3h7l9E=; b=uGCcqEcz2wuF8Z2ZQa+kC2/zjvPpi8Ku8zFNo5jWAbHoxEVKBYT/x3eMRKuLVgOlEg 2+ZHoZMgEFtM7NPR6XTvwbkWixoLiNmwi+TKT4TNj8L1JDI8kEIgc2hGDRYO3dnxnezh CyZqp6EqPdNLYkMXzAUXK739H7nYQX8CxHFQFpH8mi9yWm8JCg9vKtbk6nGfs2DB8e/9 /VszrZZ7aWkU24lhzRjw4J13NB1RZ0gSpJ87gT7XYLQtZKP3ZbRT6OLnr8jLpIWEH5Ls 8XcQ/JyFwv565Pe5Tq6Vpc0e//TZVUmJ9qUyY7WZEk73NA3YbLB35c7VFzwwpLKK47+z Fgtw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f15-v6si2593134plk.245.2018.02.21.11.14.21; Wed, 21 Feb 2018 11:14:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752369AbeBUS0L (ORCPT + 99 others); Wed, 21 Feb 2018 13:26:11 -0500 Received: from mx2.suse.de ([195.135.220.15]:44118 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751890AbeBUS0J (ORCPT ); Wed, 21 Feb 2018 13:26:09 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 8142BAD11; Wed, 21 Feb 2018 18:26:08 +0000 (UTC) Date: Wed, 21 Feb 2018 19:25:53 +0100 From: Borislav Petkov To: Ashok Raj Cc: X86 ML , LKML , Thomas Gleixner , Ingo Molnar , Tony Luck , Andi Kleen , Tom Lendacky , Arjan Van De Ven Subject: Re: [PATCH 2/3] x86/microcode/intel: Perform a cache flush before ucode update. Message-ID: <20180221182553.GD16888@pd.tnic> References: <1519231784-9941-1-git-send-email-ashok.raj@intel.com> <1519231784-9941-3-git-send-email-ashok.raj@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1519231784-9941-3-git-send-email-ashok.raj@intel.com> User-Agent: Mutt/1.9.3 (2018-01-21) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Feb 21, 2018 at 08:49:43AM -0800, Ashok Raj wrote: > Microcode updates can be safer if the caches are clean. > Some of the issues around in certain Broadwell parts > can be addressed by doing a full cache flush. Take that text... > > Signed-off-by: Ashok Raj > Cc: X86 ML > Cc: LKML > Cc: Thomas Gleixner > Cc: Ingo Molnar > Cc: Tony Luck > Cc: Andi Kleen > Cc: Boris Petkov > Cc: Tom Lendacky > Cc: Arjan Van De Ven > --- > arch/x86/kernel/cpu/microcode/intel.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c > index eff80df..5d32724 100644 > --- a/arch/x86/kernel/cpu/microcode/intel.c > +++ b/arch/x86/kernel/cpu/microcode/intel.c > @@ -589,6 +589,7 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) > if (!mc) > return 0; > ... and put it here as a comment. > + wbinvd(); This definitely needs to be native_wbinvd(). Early mode don't love pvops. > /* write microcode via MSR 0x79 */ > native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); > > @@ -805,6 +806,7 @@ static enum ucode_state apply_microcode_intel(int cpu) > return UCODE_OK; > } Ditto. > + wbinvd(); > /* write microcode via MSR 0x79 */ > wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); > > -- > 2.7.4 > -- Regards/Gruss, Boris. SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg) --