Received: by 10.223.185.116 with SMTP id b49csp1538246wrg; Wed, 21 Feb 2018 21:51:12 -0800 (PST) X-Google-Smtp-Source: AH8x226/2opzx/ShtiRuizoLyZ1umnlo+eph7ZZCjqpiWxEiTFAKjSOGMWr+IFufGNx/4u4qeXHk X-Received: by 2002:a17:902:6c06:: with SMTP id q6-v6mr5574575plk.142.1519278671978; Wed, 21 Feb 2018 21:51:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519278671; cv=none; d=google.com; s=arc-20160816; b=Q9R1fGo/qC5GFoAC1x2l0NL6FpKW3RxJmxO3eJbyZrMo2Dbb3FVA9l6a363tKJpI8f S9gvJAyhiq1vrzkOX3fWo98M80Z4E9kWKYmNdso6VWPOx3/DFn22MwKsAZq2MTPrqwaw thdqHSrSvurCZ4dloGSUCoOYMWiAZAP6vMh/qshpuPtowzOM0qhu22v2JpIAGSG0CZ9O dJ+OSYNiGPnxqCtMqBJhaidAz98X+tQ6BlmAjuFNe+47tt4yp7AiBT7NhZyu0Uu6LJ2q JlfeJqAy8Ti2io/m3BFNpf72Itm+x/5LuHb+l97UNOu0ofJAGwcbBTYeRXHThmeH/tKI +yYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=08vUIgqntUDoHRK16CsqOVUs5rnqJOsHd7Fy1qi7ubA=; b=bXVuZ8xm4s+pd2cBlN5z182ym6r3UCIwjPwaxxmU4ChtISEcOkJCAmb0XjDUOlTg0F 0QiI4wAnANP2qH9XDJ3Jxj9fRIVc00VgbKhptUSCTp6f3xhv8ePuLiyICILVtmoUBbVS fOD2LxHkKgYa5iQyeiqpg55jTkiOdSc1TsfSE+xeq1zyQqNsJPnzuFpMJoK4HGSkPo4y c0r3/T86fR3Mlc9oFoxhx/A2SfscLhL6tYiszgBfvIYgobHGj+c5T3vH2YIqk9G3wXOT tM6NspTw6kD6f9DUw2Kv5+pZLtyj5y3qnYX8P40B7fwuWPZwv6N90SGVBgQ/OxApO6Wt BSDw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d9si1194021pfb.104.2018.02.21.21.50.58; Wed, 21 Feb 2018 21:51:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752487AbeBVFtN (ORCPT + 99 others); Thu, 22 Feb 2018 00:49:13 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:28463 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751444AbeBVFtG (ORCPT ); Thu, 22 Feb 2018 00:49:06 -0500 X-UUID: 26e2bfb36e4d4598a4900965954f9b38-20180222 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1716759898; Thu, 22 Feb 2018 13:49:01 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 22 Feb 2018 13:49:00 +0800 Received: from mtkslt210.mediatek.inc (10.21.14.14) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Thu, 22 Feb 2018 13:49:00 +0800 From: Weiyi Lu To: Matthias Brugger , Stephen Boyd , Mike Turquette , Rob Herring CC: James Liao , Fan Chen , , , , , , , Weiyi Lu Subject: [PATCH v1 4/5] arm64: dts: add clock device nodes of MT2712 Date: Thu, 22 Feb 2018 13:48:50 +0800 Message-ID: <20180222054851.26096-6-weiyi.lu@mediatek.com> X-Mailer: git-send-email 2.12.5 In-Reply-To: <20180222054851.26096-1-weiyi.lu@mediatek.com> References: <20180222054851.26096-1-weiyi.lu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org add new clocks according to ECO design change Signed-off-by: Weiyi Lu --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index fdf66f4fe7c3..d7688bc9db1b 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -199,6 +199,34 @@ clock-output-names = "clkaud_ext_i_2"; }; + clki2si0_mck_i: oscillator@6 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <30000000>; + clock-output-names = "clki2si0_mck_i"; + }; + + clki2si1_mck_i: oscillator@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <30000000>; + clock-output-names = "clki2si1_mck_i"; + }; + + clki2si2_mck_i: oscillator@8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <30000000>; + clock-output-names = "clki2si2_mck_i"; + }; + + clktdmin_mclk_i: oscillator@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <30000000>; + clock-output-names = "clktdmin_mclk_i"; + }; + timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; -- 2.12.5