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[209.132.180.67]) by mx.google.com with ESMTP id 133si225534pfy.347.2018.02.22.08.05.01; Thu, 22 Feb 2018 08:05:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=LqlgHGwo; dkim=pass header.i=@codeaurora.org header.s=default header.b=ldzOTj8J; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933243AbeBVQC7 (ORCPT + 99 others); Thu, 22 Feb 2018 11:02:59 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:55798 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933068AbeBVQC5 (ORCPT ); Thu, 22 Feb 2018 11:02:57 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id AB51560A50; Thu, 22 Feb 2018 16:02:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1519315376; bh=ULmHyF/eZAEdnQoxuUPmW6o8vHCTszsSk9fmZcT0UKM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LqlgHGwommtKChEyaE+DrSJchd/dzQChlUB0EP4ruoOkVa7jZylBWAR9IWLzmRWbP Z2j4u/w5n8/dJjm0p/RnuNfpWc8VSwyHacr+DfTOmLD8mj+2F3h/g8UDjCjbG0cDiV 8piBpEGm4oTOTDLe/1mtzF3q4OPe1NWDohAkq3z0= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from blr-ubuntu-poza.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.1 with cipher ECDHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: poza@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 9B2F360F78; Thu, 22 Feb 2018 16:02:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1519315368; bh=ULmHyF/eZAEdnQoxuUPmW6o8vHCTszsSk9fmZcT0UKM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ldzOTj8JR5VsT69kDlO2rDpVNWsF6QJehsHWPOPTYJl3rRdTIbRWHix6pw+BWyBL9 rAtF870FFemw2HbySoaqrSXww4jWq6IKik1n5YkpFTlj+XagKrlQcdhvhgGt7ga1h5 R7Ci/q7K3hopGbxc08qm95RZwcao3jcxBKZkEEIw= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9B2F360F78 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=poza@codeaurora.org From: Oza Pawandeep To: Bjorn Helgaas , Philippe Ombredanne , Thomas Gleixner , Greg Kroah-Hartman , Kate Stewart , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Dongdong Liu , Keith Busch , Wei Zhang , Sinan Kaya , Timur Tabi Cc: Oza Pawandeep Subject: [PATCH v10 6/7] PCI: Unify wait for link active into generic pci Date: Thu, 22 Feb 2018 21:32:11 +0530 Message-Id: <1519315332-26852-7-git-send-email-poza@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519315332-26852-1-git-send-email-poza@codeaurora.org> References: <1519315332-26852-1-git-send-email-poza@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Clients such as pciehp, dpc are using pcie_wait_link_active, which waits till the link becomes active or inactive. Made generic function and moved it to drivers/pci/pci.c Signed-off-by: Oza Pawandeep diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 18a42f8..de9b0ea 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -231,25 +231,11 @@ bool pciehp_check_link_active(struct controller *ctrl) return ret; } -static void __pcie_wait_link_active(struct controller *ctrl, bool active) +static bool pcie_wait_link_active(struct controller *ctrl) { - int timeout = 1000; - - if (pciehp_check_link_active(ctrl) == active) - return; - while (timeout > 0) { - msleep(10); - timeout -= 10; - if (pciehp_check_link_active(ctrl) == active) - return; - } - ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n", - active ? "set" : "cleared"); -} + struct pci_dev *pdev = ctrl_dev(ctrl); -static void pcie_wait_link_active(struct controller *ctrl) -{ - __pcie_wait_link_active(ctrl, true); + return pci_wait_for_link(pdev, true); } static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index f6a4dd1..5440696 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4176,6 +4176,40 @@ static int pci_pm_reset(struct pci_dev *dev, int probe) return 0; } +/** + * pci__wait_for_link - Wait for link till its active/inactive + * @pdev: Bridge device + * @active: waiting for active or inactive ? + * + * Use this to wait till link becomes active or inactive. + */ +bool pci_wait_for_link(struct pci_dev *pdev, bool active) +{ + int timeout = 1000; + bool ret; + u16 lnk_status; + + pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); + ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); + + while ((ret != active) && (timeout > 0)) { + msleep(10); + timeout -= 10; + pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); + ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); + } + + if (ret == active) + return true; + + dev_printk(KERN_DEBUG, &pdev->dev, + "Data Link Layer Link Active not %s in 1000 msec\n", + active ? "set" : "cleared"); + + return false; +} +EXPORT_SYMBOL(pci_wait_for_link); + void pci_reset_secondary_bus(struct pci_dev *dev) { u16 ctrl; diff --git a/drivers/pci/pcie/pcie-dpc.c b/drivers/pci/pcie/pcie-dpc.c index 208b427..0524bd3 100644 --- a/drivers/pci/pcie/pcie-dpc.c +++ b/drivers/pci/pcie/pcie-dpc.c @@ -122,19 +122,9 @@ static int dpc_wait_rp_inactive(struct dpc_dev *dpc) static void dpc_wait_link_inactive(struct dpc_dev *dpc) { - unsigned long timeout = jiffies + HZ; struct pci_dev *pdev = dpc->dev->port; - struct device *dev = &dpc->dev->device; - u16 lnk_status; - pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); - while (lnk_status & PCI_EXP_LNKSTA_DLLLA && - !time_after(jiffies, timeout)) { - msleep(10); - pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); - } - if (lnk_status & PCI_EXP_LNKSTA_DLLLA) - dev_warn(dev, "Link state not disabled for DPC event\n"); + pci_wait_for_link(pdev, false); } /** diff --git a/include/linux/pci.h b/include/linux/pci.h index 024a1be..cb674c3 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1195,6 +1195,7 @@ int pci_add_ext_cap_save_buffer(struct pci_dev *dev, int pci_request_selected_regions(struct pci_dev *, int, const char *); int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); void pci_release_selected_regions(struct pci_dev *, int); +bool pci_wait_for_link(struct pci_dev *pdev, bool active); /* drivers/pci/bus.c */ struct pci_bus *pci_bus_get(struct pci_bus *bus); -- Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc., a Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.