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Date:   Thu, 22 Feb 2018 15:14:52 -0800 (PST)
Subject:     Re: [PATCH RFC] riscv/barrier: Define __smp_{mb,rmb,wmb}
In-Reply-To: <1519121848-28582-1-git-send-email-parri.andrea@gmail.com>
CC:     albert@sifive.com, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org, parri.andrea@gmail.com
From:   Palmer Dabbelt <palmer@sifive.com>
To:     parri.andrea@gmail.com
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On Tue, 20 Feb 2018 02:17:28 PST (-0800), parri.andrea@gmail.com wrote:
> Introduce __smp_{mb,rmb,wmb}, and rely on the generic definitions
> for smp_{mb,rmb,wmb}. A first consequence is that smp_{mb,rmb,wmb}
> map to a compiler barrier on !SMP (while their definition remains
> unchanged on SMP). As a further consequence, smp_load_acquire and
> smp_store_release have "fence rw,rw" instead of "fence iorw,iorw".
>
> Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
> ---
>  arch/riscv/include/asm/barrier.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h
> index c0319cbf1eec5..5510366d169ae 100644
> --- a/arch/riscv/include/asm/barrier.h
> +++ b/arch/riscv/include/asm/barrier.h
> @@ -34,9 +34,9 @@
>  #define wmb()		RISCV_FENCE(ow,ow)
>
>  /* These barriers do not need to enforce ordering on devices, just memory. */
> -#define smp_mb()	RISCV_FENCE(rw,rw)
> -#define smp_rmb()	RISCV_FENCE(r,r)
> -#define smp_wmb()	RISCV_FENCE(w,w)
> +#define __smp_mb()	RISCV_FENCE(rw,rw)
> +#define __smp_rmb()	RISCV_FENCE(r,r)
> +#define __smp_wmb()	RISCV_FENCE(w,w)
>
>  /*
>   * This is a very specific barrier: it's currently only used in two places in

Thanks!  I'm going to take this for the next RC.