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Fri, 23 Feb 2018 00:34:13 -0800 (PST) MIME-Version: 1.0 Received: by 10.25.72.134 with HTTP; Fri, 23 Feb 2018 00:34:12 -0800 (PST) In-Reply-To: References: <1519221027-4028-2-git-send-email-radoslaw.pietrzyk@gmail.com> From: =?UTF-8?Q?Rados=C5=82aw_Pietrzyk?= Date: Fri, 23 Feb 2018 09:34:12 +0100 Message-ID: Subject: Re: [1/2] ARM: irqchip: stm32: Optimizes and cleans up stm32-exti irq_domain To: Ludovic BARRE Cc: Thomas Gleixner , Jason Cooper , Marc Zyngier , Maxime Coquelin , Alexandre Torgue , Linus Walleij , Benjamin Gaignard , Philipp Zabel , open list , "moderated list:ARM/STM32 ARCHITECTURE" , linux-gpio@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Ludovic, Please check latest v2 patches series and let me know if it works on stm32h7 as it does on stm32f4 2018-02-22 12:01 GMT+01:00 Rados=C5=82aw Pietrzyk : > Hi Ludovic, > I have tested on stm32f429-disco and it works without a problem. > handle_edge_irq is not used in current implementation because it is > substituted by handle_simple_irq in an alloc callback either way which > causes that irq_ack callback is not invoked as well (acking is done in > chained handler). > > 2018-02-22 11:55 GMT+01:00 Ludovic BARRE : >> Hi Radek >> >> I've tested your change on stm32h743i-eval.dts board >> and gpio-keys tests are not functional. >> No interrupt occurs when we push or release button >> (cat /proc/interrupt). >> >> Board: stm32h743i-eval.dts >> Test description: gpio-keys (gpioc 13 =3D> exti 13), with gpio or interr= upt >> property. >> >> comment below >> >> >> On 02/21/2018 02:50 PM, radek wrote: >>> >>> - allocates generic chip with handle_simple_irq >>> which simplifies irq_domain_ops.alloc callback >>> - removes ack register from generic chip which is not used for >>> handle_simple_irq as acking is done in a chained handler >>> - removes unneeded irq_domain_ops.xlate callback >>> >>> Signed-off-by: Radoslaw Pietrzyk >>> --- >>> drivers/irqchip/irq-stm32-exti.c | 10 +--------- >>> 1 file changed, 1 insertion(+), 9 deletions(-) >>> >>> diff --git a/drivers/irqchip/irq-stm32-exti.c >>> b/drivers/irqchip/irq-stm32-exti.c >>> index 36f0fbe..42e74e3 100644 >>> --- a/drivers/irqchip/irq-stm32-exti.c >>> +++ b/drivers/irqchip/irq-stm32-exti.c >>> @@ -176,16 +176,12 @@ static int stm32_irq_set_wake(struct irq_data *da= ta, >>> unsigned int on) >>> static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq, >>> unsigned int nr_irqs, void *data) >>> { >>> - struct irq_chip_generic *gc; >>> struct irq_fwspec *fwspec =3D data; >>> irq_hw_number_t hwirq; >>> hwirq =3D fwspec->param[0]; >>> - gc =3D irq_get_domain_generic_chip(d, hwirq); >>> irq_map_generic_chip(d, virq, hwirq); >>> - irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc, >>> - handle_simple_irq, NULL, NULL); >>> return 0; >>> } >>> @@ -200,7 +196,6 @@ static void stm32_exti_free(struct irq_domain *d, >>> unsigned int virq, >>> struct irq_domain_ops irq_exti_domain_ops =3D { >>> .map =3D irq_map_generic_chip, >>> - .xlate =3D irq_domain_xlate_onetwocell, >>> .alloc =3D stm32_exti_alloc, >>> .free =3D stm32_exti_free, >>> }; >>> @@ -231,7 +226,7 @@ __init stm32_exti_init(const struct stm32_exti_bank >>> **stm32_exti_banks, >>> } >>> ret =3D irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1= , >>> "exti", >>> - handle_edge_irq, clr, 0, 0= ); >>> + handle_simple_irq, clr, 0, >>> 0); >> >> >> EXTI hardware block is trigged on pulse event rising or failing edge. >> Why do you change to handle_simple_irq ? >> >>> if (ret) { >>> pr_err("%pOF: Could not allocate generic interrupt >>> chip.\n", >>> node); >>> @@ -246,13 +241,10 @@ __init stm32_exti_init(const struct stm32_exti_ba= nk >>> **stm32_exti_banks, >>> gc->reg_base =3D base; >>> gc->chip_types->type =3D IRQ_TYPE_EDGE_BOTH; >>> - gc->chip_types->chip.irq_ack =3D irq_gc_ack_set_bit; >>> gc->chip_types->chip.irq_mask =3D irq_gc_mask_clr_bit; >>> gc->chip_types->chip.irq_unmask =3D irq_gc_mask_set_bit= ; >>> gc->chip_types->chip.irq_set_type =3D stm32_irq_set_typ= e; >>> gc->chip_types->chip.irq_set_wake =3D stm32_irq_set_wak= e; >>> - gc->chip_types->regs.ack =3D stm32_bank->pr_ofst; >>> - gc->chip_types->regs.mask =3D stm32_bank->imr_ofst; >>> gc->private =3D (void *)stm32_bank; >>> /* Determine number of irqs supported */ >>> >> >> BR >> Ludo