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[209.132.180.67]) by mx.google.com with ESMTP id t9si3131410pge.540.2018.02.24.08.45.50; Sat, 24 Feb 2018 08:46:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OijL3mh+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751665AbeBXQoB (ORCPT + 99 others); Sat, 24 Feb 2018 11:44:01 -0500 Received: from mail-it0-f65.google.com ([209.85.214.65]:34103 "EHLO mail-it0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751422AbeBXQn7 (ORCPT ); Sat, 24 Feb 2018 11:43:59 -0500 Received: by mail-it0-f65.google.com with SMTP id a203so7803881itd.1 for ; Sat, 24 Feb 2018 08:43:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=H5n+r424YeVP44fLpGzTI/zIdQUEHEk2y4Ij72BYWd4=; b=OijL3mh+GyKZ6kalX+hGwDZ3j1A21ZEbc6iaWpAKxqLoz5HXuBbEErZhXR3E/zJec/ nR0S7yFrG2mgNFYJv9qFF1UkVcwLLstAvZ9wGzr5FzmuV27v2/NY+GyPMLP53JQVW4Wy GHvlDE1bSwSXGqdISuh/vHhYNMXcgA1FSTNsA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=H5n+r424YeVP44fLpGzTI/zIdQUEHEk2y4Ij72BYWd4=; b=WtTmUbNGwXPt+8b8Qi4BGlCZObe0nsupiKB7SDn58FEDsgMLTD23kyDdPzbZjx12nq cjk6RULa9yIKxMifv93wHwOkqbw0ouywhgHDkkt321YutjgYhEIaLOhcPvNAZGRUM6an edKLj0OxHsJbZjanTP8S4f/bm+ONO9zfKh6HqwWkDu1hyzdDNR+e/E7TkP+L/u3Xz07V R30T5Da7PhCio++py5YqdA3T4JRx25xefwOxjUu9W9aBiZ+finXeVlw+rqLY779FCGpE UbKCe2BK0fKw4Bbv8BwjLJWFz3XJ4hZd8p5rsI8Q75psipiww84+1H4XUDX31uWTN17e E1vg== X-Gm-Message-State: APf1xPAwl5EgfnqlISBISh8uejMVDiQDQ+S48Df844uJ1kW1HN8ZmFHJ niUUBhiLi2afTTuMHeSQWf/LcGUKSOKrMcoz1XlL8A== X-Received: by 10.36.217.22 with SMTP id p22mr6591084itg.106.1519490638833; Sat, 24 Feb 2018 08:43:58 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.138.209 with HTTP; Sat, 24 Feb 2018 08:43:58 -0800 (PST) In-Reply-To: <20180223200333.6410-8-Yazen.Ghannam@amd.com> References: <20180223200333.6410-1-Yazen.Ghannam@amd.com> <20180223200333.6410-8-Yazen.Ghannam@amd.com> From: Ard Biesheuvel Date: Sat, 24 Feb 2018 16:43:58 +0000 Message-ID: Subject: Re: [PATCH 7/8] efi: Decode IA32/X64 MS Check structure To: Yazen Ghannam Cc: linux-efi@vger.kernel.org, Linux Kernel Mailing List , Borislav Petkov , "the arch/x86 maintainers" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23 February 2018 at 20:03, Yazen Ghannam wrote: > From: Yazen Ghannam > > The IA32/X64 MS Check structure varies from the other Check structures > in the the bit positions of its fields, and it includes an additional > "Error Type" field. > > Decode the MS Check structure in a separate function. > > Based on UEFI 2.7 Table 260. IA32/X64 MS Check Field Description. > > Cc: # 4.16.x > Signed-off-by: Yazen Ghannam > --- > drivers/firmware/efi/cper-x86.c | 55 ++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 54 insertions(+), 1 deletion(-) > > diff --git a/drivers/firmware/efi/cper-x86.c b/drivers/firmware/efi/cper-x86.c > index df4cf6221d8e..02b1b424f537 100644 > --- a/drivers/firmware/efi/cper-x86.c > +++ b/drivers/firmware/efi/cper-x86.c > @@ -60,6 +60,20 @@ > #define CHECK_BUS_TIME_OUT BIT_ULL(32) > #define CHECK_BUS_ADDR_SPACE(check) ((check & GENMASK_ULL(34, 33)) >> 33) > > +#define CHECK_VALID_MS_ERR_TYPE BIT_ULL(0) > +#define CHECK_VALID_MS_PCC BIT_ULL(1) > +#define CHECK_VALID_MS_UNCORRECTED BIT_ULL(2) > +#define CHECK_VALID_MS_PRECISE_IP BIT_ULL(3) > +#define CHECK_VALID_MS_RESTARTABLE_IP BIT_ULL(4) > +#define CHECK_VALID_MS_OVERFLOW BIT_ULL(5) > + > +#define CHECK_MS_ERR_TYPE(check) ((check & GENMASK_ULL(18, 16)) >> 16) Parens > +#define CHECK_MS_PCC BIT_ULL(19) > +#define CHECK_MS_UNCORRECTED BIT_ULL(20) > +#define CHECK_MS_PRECISE_IP BIT_ULL(21) > +#define CHECK_MS_RESTARTABLE_IP BIT_ULL(22) > +#define CHECK_MS_OVERFLOW BIT_ULL(23) > + > enum err_types { > ERR_TYPE_CACHE = 0, > ERR_TYPE_TLB, > @@ -114,19 +128,58 @@ static const char * const ia_check_bus_addr_space_strs[] = { > "Other Transaction", > }; > > +static const char * const ia_check_ms_error_type_strs[] = { > + "No Error", > + "Unclassified", > + "Microcode ROM Parity Error", > + "External Error", > + "FRC Error", > + "Internal Unclassified", > +}; > + > static inline void print_bool(char *str, const char *pfx, u64 check, u64 bit) > { > printk("%s%s: %s\n", pfx, str, (check & bit) ? "true" : "false"); > } > > +static void print_err_info_ms(const char *pfx, u16 validation_bits, u64 check) > +{ > + if (validation_bits & CHECK_VALID_MS_ERR_TYPE) { > + u8 err_type = CHECK_MS_ERR_TYPE(check); > + > + printk("%sError Type: %u, %s\n", pfx, err_type, > + err_type < ARRAY_SIZE(ia_check_ms_error_type_strs) ? > + ia_check_ms_error_type_strs[err_type] : "unknown"); > + } > + > + if (validation_bits & CHECK_VALID_MS_PCC) > + print_bool("Processor Context Corrupt", pfx, check, CHECK_MS_PCC); > + > + if (validation_bits & CHECK_VALID_MS_UNCORRECTED) > + print_bool("Uncorrected", pfx, check, CHECK_MS_UNCORRECTED); > + > + if (validation_bits & CHECK_VALID_MS_PRECISE_IP) > + print_bool("Precise IP", pfx, check, CHECK_MS_PRECISE_IP); > + > + if (validation_bits & CHECK_VALID_MS_RESTARTABLE_IP) > + print_bool("Restartable IP", pfx, check, CHECK_MS_RESTARTABLE_IP); > + > + if (validation_bits & CHECK_VALID_MS_OVERFLOW) > + print_bool("Overflow", pfx, check, CHECK_MS_OVERFLOW); > +} > + > static void print_err_info(const char *pfx, enum err_types err_type, u64 check) > { > u16 validation_bits = CHECK_VALID_BITS(check); > > printk("%sValidation Bits: 0x%04x\n", pfx, validation_bits); > > + /* > + * The MS Check structure varies a lot from the others, so use a > + * separate function for decoding. > + */ > if (err_type == ERR_TYPE_MS) > - return; > + return print_err_info_ms(pfx, validation_bits, check); > > if (validation_bits & CHECK_VALID_TRANS_TYPE) { > u8 trans_type = CHECK_TRANS_TYPE(check); > -- > 2.14.1 >