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[209.132.180.67]) by mx.google.com with ESMTP id s9-v6si5134142plr.57.2018.02.25.06.37.44; Sun, 25 Feb 2018 06:37:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751746AbeBYOhG (ORCPT + 99 others); Sun, 25 Feb 2018 09:37:06 -0500 Received: from foss.arm.com ([217.140.101.70]:41442 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751638AbeBYOhE (ORCPT ); Sun, 25 Feb 2018 09:37:04 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CEEF180D; Sun, 25 Feb 2018 06:37:03 -0800 (PST) Received: from salmiak (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7A4CB3F53D; Sun, 25 Feb 2018 06:37:01 -0800 (PST) Date: Sun, 25 Feb 2018 14:36:53 +0000 From: Mark Rutland To: Saravana Kannan Cc: Suzuki K Poulose , will.deacon@arm.com, robh@kernel.org, sudeep.holla@arm.com, mathieu.poirier@linaro.org, peterz@infradead.org, jonathan.cameron@huawei.com, linux-kernel@vger.kernel.org, marc.zyngier@arm.com, leo.yan@linaro.org, frowand.list@gmail.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v11 8/8] perf: ARM DynamIQ Shared Unit PMU support Message-ID: <20180225143653.peb4quk3ha5h3t5x@salmiak> References: <20180102112533.13640-1-suzuki.poulose@arm.com> <20180102112533.13640-9-suzuki.poulose@arm.com> <5A90B77E.8040105@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5A90B77E.8040105@codeaurora.org> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Feb 23, 2018 at 04:53:18PM -0800, Saravana Kannan wrote: > On 01/02/2018 03:25 AM, Suzuki K Poulose wrote: > > +static void dsu_pmu_event_update(struct perf_event *event) > > +{ > > + struct hw_perf_event *hwc = &event->hw; > > + u64 delta, prev_count, new_count; > > + > > + do { > > + /* We may also be called from the irq handler */ > > + prev_count = local64_read(&hwc->prev_count); > > + new_count = dsu_pmu_read_counter(event); > > + } while (local64_cmpxchg(&hwc->prev_count, prev_count, new_count) != > > + prev_count); > > + delta = (new_count - prev_count) & DSU_PMU_COUNTER_MASK(hwc->idx); > > + local64_add(delta, &event->count); > > +} > > + > > +static void dsu_pmu_read(struct perf_event *event) > > +{ > > + dsu_pmu_event_update(event); > > +} > I sent out a patch that'll allow PMUs to set an event flag to avoid > unnecessary smp calls when the event can be read from any CPU. You could > just always set that if you can't have multiple DSU's running the kernel (I > don't know if the current ARM designs support having multiple DSUs in a > SoC/system) or set it if associated_cpus == cpu_present_mask. As-is, that won't be safe, given the read function calls the event_update() function, which has side-effects on hwc->prec_count and event->count. Those need to be serialized somehow. Thanks, Mark.