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[209.132.180.67]) by mx.google.com with ESMTP id z7si4885366pgv.473.2018.02.25.19.03.37; Sun, 25 Feb 2018 19:03:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SuYyUYxw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752134AbeBZDBX (ORCPT + 99 others); Sun, 25 Feb 2018 22:01:23 -0500 Received: from mail-oi0-f68.google.com ([209.85.218.68]:46672 "EHLO mail-oi0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751945AbeBZDBS (ORCPT ); Sun, 25 Feb 2018 22:01:18 -0500 Received: by mail-oi0-f68.google.com with SMTP id x12so9610752oie.13 for ; Sun, 25 Feb 2018 19:01:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=lIgL/7aS5V2hfrzrtb8RGLqvgbbO6QMQOWwYF1WCy+Y=; b=SuYyUYxwO+43eg/AFFa3N3QxnbSeFnlUNBhYsM9uBWKX2xzN9Nt4gal5p5Rf77l21f zOyeMapqlFbWrGkzN8mKSyaxe/Z63KXzycxGANhwQ1NsAPUkMoTHxopHjguruiA0N6ae CvGwJWO9Zh7VHyRJ2BmpwSU/bl9VS4LiSF1vA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=lIgL/7aS5V2hfrzrtb8RGLqvgbbO6QMQOWwYF1WCy+Y=; b=scdtJDsjWh7/P605F9H1MIDJAwfShnKB5zoKpO5LtsROC0Sq5TuMci6doOiu9zF7FS 64ueNjhxsPTRSjAVNU4x1PffceXTJcZvvnTh0YQXKBn9AGoULRw18YRDgQvnuHXfWE3c y1VVOpwRMuyyWGTHaV8kdDvd7Dny673zA3lU8E/kiNzepHCgjW0lzGz6DyHSoZY2i8Dr 0ecWrf9FkXk9y0ETIrSHEUAHxFAyEuNW8juO+OtzqT92F+mBJnJChnMzSLoqU/7wAjUW GkKvSkydjMBGfdty2zmbB26wM8AQZ2t2XHowHrpHh3cdH/shmMPoa/LYZqcMW/XfXegD q3QQ== X-Gm-Message-State: APf1xPARgV1ni+UzGtTZJ/hIkb5M7GySvBAYNprOodZMUaHBFugvJI6j +MM8IIe4Cv7BvMgJSDDsGt2k+bXNxrafzxX3p0tGpw== X-Received: by 10.202.59.197 with SMTP id i188mr5491892oia.177.1519614077595; Sun, 25 Feb 2018 19:01:17 -0800 (PST) MIME-Version: 1.0 Received: by 10.157.96.5 with HTTP; Sun, 25 Feb 2018 19:01:17 -0800 (PST) In-Reply-To: References: <334505d3a13a73ad347427b408ed581832434289.1519468782.git.baolin.wang@linaro.org> From: Baolin Wang Date: Mon, 26 Feb 2018 11:01:17 +0800 Message-ID: Subject: Re: [PATCH v2 3/3] gpio: Add Spreadtrum PMIC EIC driver support To: Andy Shevchenko Cc: Linus Walleij , Rob Herring , Mark Rutland , devicetree , Linux Kernel Mailing List , "open list:GPIO SUBSYSTEM" , Mark Brown Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Andy, On 25 February 2018 at 20:19, Andy Shevchenko wrote: > On Sat, Feb 24, 2018 at 12:44 PM, Baolin Wang wrote: >> The Spreadtrum PMIC EIC controller contains only one bank of debounce EIC, >> and this bank contains 16 EICs. Each EIC can only be used as input mode, >> as well as supporting the debounce and the capability to trigger interrupts >> when detecting input signals. > >> +/* >> + * These registers are modified under the irq bus lock and cached to avoid >> + * unnecessary writes in bus_sync_unlock. >> + */ >> +enum { REG_IEV, REG_IE, REG_TRIG, CACHE_NR_REGS }; > > One item per line. Sure. > >> +static int sprd_pmic_eic_direction_input(struct gpio_chip *chip, >> + unsigned int offset) >> +{ >> + /* EICs are always input, nothing need to do here. */ >> + return 0; >> +} >> + >> +static void sprd_pmic_eic_set(struct gpio_chip *chip, unsigned int offset, >> + int value) >> +{ >> + /* EICs are always input, nothing need to do here. */ >> +} > > Remove both. > > Look at what GPIO core does. I've checked the GPIO core, we need the sprd_pmic_eic_direction_input() returns 0, since user can set GPIOD_IN flag when requesting one GPIO, otherwise it will return errors. We also need one dummy sprd_pmic_eic_set() when setting debounce for one GPIO, otherwise it will return errors. > >> + value |= debounce / 1000; > > Possible overflow. OK. I should & SPRD_PMIC_EIC_DBC_MASK. > >> + for (n = 0; n < chip->ngpio; n++) { >> + if (!(BIT(n) & val)) > > for_each_set_bit(). > > At some point you may need just to go across lib/ in the kernel and > see what we have there. I've considered the for_each_set_bit(), it need one 'unsigned long' type parameter, but we get the value from regmap is 'u32' type. So we need one extra conversion from 'u32' to 'unsigned long' like: unsigned long reg = val; for_each_set_bit(n, ®, chip->ngpio) { ....... } If you like this conversion, then I can change to use for_each_set_bit(). Thanks. -- Baolin.wang Best Regards