Received: by 10.223.185.116 with SMTP id b49csp3498007wrg; Mon, 26 Feb 2018 00:37:44 -0800 (PST) X-Google-Smtp-Source: AH8x227tscfvbt6DInnkVQIG+qYk59Pq8goZytQqCV8FXeMopCRmZGF4GPZv3IKBA0rRKpve6JiB X-Received: by 2002:a17:902:8302:: with SMTP id bd2-v6mr9564274plb.295.1519634264433; Mon, 26 Feb 2018 00:37:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519634264; cv=none; d=google.com; s=arc-20160816; b=mGFNDXq0683bAHgBYzNg6NUaxp+fuIqg+BvQ8gtPjWFZA27a9XLYSREHHPKNTmwk7G jsWjCZxTlUnzb7nAzziB8O3ZsalMz7Vm5Gbmk3GIJjwdfbwMfrRg9dBEaltk8QpXQvl2 C0h+mM4VRGGscOXwmoKjsw6eutBwwRQcqtmsQQjfSvh9arRliKe6RF9j4mnjZD8Xa6e2 gNxFO7TGCgkVny0lsci5AMgSJ+CW9DERQTZhrDV9YsbczyCtT26/DYgwzZuS2TD5PCmp ADpVMB1me57ZGkP8VV3UwK5Nz2i/wtVQ3oaRotUtLOqpkf4G7Pv9jdR7U/1UoUJIW05/ uZxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=wm/7KbzfL3VedC+gcgSIStbrpd2IKqkAYf0vdKvVexs=; b=FmxQTZyrIJaFPuUO3yfUmrqF9iuuoOc9t/Pa7m8LBno6wFmfWMkcwF5wAXGTX4wtlZ neYvuGhGAbeTng88UL2juksUazMmPsf7yf4yZtwHE+FAWEVWwVf0xXzexqwkPWaazhdr +qJpbizb7DtWOGgpcNVuRJD0P+3hggQ3LETrAOqqnNwzQPhJE8IN7xkIZQTdvJDW5Mab RLTIBQ1lWAvnqhC7LyEg9ziEd1xmJu4pDeFzaFaoA3uNOnFkjkHEpAt+Jv+9eBOpSbXQ Yv6l06IlzJfIOri2k+9QMBopEQNJk0SyJpwPT0dlvNGacpCJmXpXGELUaTqftgRlx73T qAxA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f31-v6si6455327plb.636.2018.02.26.00.37.30; Mon, 26 Feb 2018 00:37:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752443AbeBZIgi (ORCPT + 99 others); Mon, 26 Feb 2018 03:36:38 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:60050 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751575AbeBZIeP (ORCPT ); Mon, 26 Feb 2018 03:34:15 -0500 X-UUID: 0971185db2ad48cd898d63a30c79b535-20180226 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 346854035; Mon, 26 Feb 2018 16:34:12 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Mon, 26 Feb 2018 16:34:10 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Mon, 26 Feb 2018 16:34:10 +0800 From: Zhiyong Tao To: , , , CC: , , , , , , , , , , , , , Zhiyong Tao Subject: [PATCH v2 2/4] arm64: dts: mt2712: add pintcrl device node. Date: Mon, 26 Feb 2018 16:34:00 +0800 Message-ID: <1519634042-12063-3-git-send-email-zhiyong.tao@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519634042-12063-1-git-send-email-zhiyong.tao@mediatek.com> References: <1519634042-12063-1-git-send-email-zhiyong.tao@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds pintcrl device node for mt2712. Signed-off-by: Zhiyong Tao --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index d7688bc..fb3b051 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include "mt2712-pinfunc.h" / { compatible = "mediatek,mt2712"; @@ -258,6 +259,23 @@ #clock-cells = <1>; }; + syscfg_pctl_a: syscfg_pctl_a@10005000 { + compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt2712-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + scpsys: scpsys@10006000 { compatible = "mediatek,mt2712-scpsys", "syscon"; #power-domain-cells = <1>; -- 1.9.1