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[94.36.191.219]) by smtp.googlemail.com with ESMTPSA id e12sm6614438edi.29.2018.02.26.03.42.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 26 Feb 2018 03:42:30 -0800 (PST) Subject: Re: [PATCH v2] KVM: X86: Allow userspace to define the microcode version To: Wanpeng Li , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Liran Alon References: <1519640239-4428-1-git-send-email-wanpengli@tencent.com> From: Paolo Bonzini Message-ID: <469812b9-d003-249a-d6d3-de74c24e4146@redhat.com> Date: Mon, 26 Feb 2018 12:42:28 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <1519640239-4428-1-git-send-email-wanpengli@tencent.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 26/02/2018 11:17, Wanpeng Li wrote: > From: Wanpeng Li > > Linux (among the others) has checks to make sure that certain features > aren't enabled on a certain family/model/stepping if the microcode version > isn't greater than or equal to a known good version. > > By exposing the real microcode version, we're preventing buggy guests that > don't check that they are running virtualized (i.e., they should trust the > hypervisor) from disabling features that are effectively not buggy. > > Suggested-by: Filippo Sironi > Cc: Paolo Bonzini > Cc: Radim Krčmář > Cc: Liran Alon > Signed-off-by: Wanpeng Li > --- > v1 -> v2: > * add MSR_IA32_UCODE_REV to emulated_msrs > > arch/x86/include/asm/kvm_host.h | 1 + > arch/x86/kvm/x86.c | 9 +++++++-- > 2 files changed, 8 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h > index 938d453..6e13f2f 100644 > --- a/arch/x86/include/asm/kvm_host.h > +++ b/arch/x86/include/asm/kvm_host.h > @@ -507,6 +507,7 @@ struct kvm_vcpu_arch { > u64 smi_count; > bool tpr_access_reporting; > u64 ia32_xss; > + u32 microcode_version; > > /* > * Paging state of the vcpu > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > index 1a3ed81..4ae9517 100644 > --- a/arch/x86/kvm/x86.c > +++ b/arch/x86/kvm/x86.c > @@ -1047,6 +1047,7 @@ static u32 emulated_msrs[] = { > MSR_SMI_COUNT, > MSR_PLATFORM_INFO, > MSR_MISC_FEATURES_ENABLES, > + MSR_IA32_UCODE_REV, > }; > > static unsigned num_emulated_msrs; > @@ -2247,7 +2248,6 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > > switch (msr) { > case MSR_AMD64_NB_CFG: > - case MSR_IA32_UCODE_REV: > case MSR_IA32_UCODE_WRITE: > case MSR_VM_HSAVE_PA: > case MSR_AMD64_PATCH_LOADER: > @@ -2255,6 +2255,10 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > case MSR_AMD64_DC_CFG: > break; > > + case MSR_IA32_UCODE_REV: > + if (msr_info->host_initiated) > + vcpu->arch.microcode_version = data >> 32; Please remove the shifts, and add the MSR_IA32_UCODE_REV version to the "feature MSRs" recently added by Tom Lendacky. Thanks, Paolo > + break; > case MSR_EFER: > return set_efer(vcpu, data); > case MSR_K7_HWCR: > @@ -2550,7 +2554,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > msr_info->data = 0; > break; > case MSR_IA32_UCODE_REV: > - msr_info->data = 0x100000000ULL; > + msr_info->data = (u64)vcpu->arch.microcode_version << 32; > break; > case MSR_MTRRcap: > case 0x200 ... 0x2ff: > @@ -8232,6 +8236,7 @@ void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) > vcpu->arch.regs_dirty = ~0; > > vcpu->arch.ia32_xss = 0; > + vcpu->arch.microcode_version = 0x1; > > kvm_x86_ops->vcpu_reset(vcpu, init_event); > } >