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[209.132.180.67]) by mx.google.com with ESMTP id q16si6644723pfh.395.2018.02.26.04.36.11; Mon, 26 Feb 2018 04:36:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752780AbeBZMf2 (ORCPT + 99 others); Mon, 26 Feb 2018 07:35:28 -0500 Received: from mga11.intel.com ([192.55.52.93]:12876 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752420AbeBZMfY (ORCPT ); Mon, 26 Feb 2018 07:35:24 -0500 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Feb 2018 04:35:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.47,396,1515484800"; d="scan'208";a="207025938" Received: from lahna.fi.intel.com (HELO lahna) ([10.237.72.157]) by fmsmga005.fm.intel.com with SMTP; 26 Feb 2018 04:35:19 -0800 Received: by lahna (sSMTP sendmail emulation); Mon, 26 Feb 2018 14:35:18 +0200 Date: Mon, 26 Feb 2018 14:35:18 +0200 From: Mika Westerberg To: Lukas Wunner Cc: Bjorn Helgaas , "Rafael J. Wysocki" , Linux PCI , Valdis Kletnieks , Mathias Nyman , Linux PM , "Rafael J. Wysocki" , Linux Kernel Mailing List , Peter Wu , Qipeng Zha , Greg Kroah-Hartman , Andreas Noever , Dave Airlie , Qi Zheng Subject: Re: [PATCH v1 2/2] PCI: Allow user to request power management of conventional and hotplug bridges Message-ID: <20180226123518.GP27191@lahna.fi.intel.com> References: <151908155159.37696.9710083237704994886.stgit@bhelgaas-glaptop.roam.corp.google.com> <151908204614.37696.12828004282495415825.stgit@bhelgaas-glaptop.roam.corp.google.com> <20180220181554.GA32228@bhelgaas-glaptop.roam.corp.google.com> <20180222131834.GA5527@wunner.de> <20180226120534.GO27191@lahna.fi.intel.com> <20180226122243.GA25450@wunner.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180226122243.GA25450@wunner.de> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.9.1 (2017-09-22) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Feb 26, 2018 at 01:22:43PM +0100, Lukas Wunner wrote: > On Mon, Feb 26, 2018 at 02:05:34PM +0200, Mika Westerberg wrote: > > On Thu, Feb 22, 2018 at 02:18:34PM +0100, Lukas Wunner wrote: > > > We do need runtime PM on hotplug ports to power off Thunderbolt > > > controllers when nothing is plugged in. That saves 1.5 W, so a > > > noticeable amount of power. I was going to respin the series one > > > of these days, I think the best I can do is continue to forbid > > > runtime PM on hotplug ports by default, but whitelist it for > > > Thunderbolt and allow manually enabling it on other platforms via > > > the command line. That way, vendors are put in a position to > > > validate their platforms for runtime PM of hotplug ports, and > > > perhaps someday we can enable it for all platforms by default, > > > but with a BIOS cut-off date. > > > > AFAIK Windows started to enable runtime PM (RTD3) for native PCIe > > hotplug ports with the latest release (I guess it's the RS3 release) but > > only when there is a special ACPI _DSD property ("HotPlugSupportInD3") > > associated with the root port. I think we can take advantage of that in > > Linux as well and I already have a patch series to enable runtime PM for > > such ports but I haven't been able to test it properly yet. > > Okay. Well it would be trivial to whitelist those ports with > device_property_present("HotPlugSupportInD3"). In how far are > your patches identical with the patches I submitted last May? My patches pretty much only touch the whitelist part not the other fixes you made for pciehp in your series. We can add those on top of your series or I can send them out separately. > I've started reworking them for v2 but that would be a waste of > time if you're working on this issue in parallel. Please continue with your v2 :) I can provide testing assistance if you need any.