Received: by 10.223.185.116 with SMTP id b49csp4045722wrg; Mon, 26 Feb 2018 10:10:52 -0800 (PST) X-Google-Smtp-Source: AH8x227nvP96RNUtjfiMvNx0a4S5aEJ+znrQBgK3Sah/PPAGCvehEDWveqcvAIS7MTw4O5uQn+ci X-Received: by 10.98.162.26 with SMTP id m26mr11413296pff.217.1519668652367; Mon, 26 Feb 2018 10:10:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519668652; cv=none; d=google.com; s=arc-20160816; b=AN975RxaUicoywi0xV62wvNEhd8bSgCXf5y+yszzB9DmxGqmk8BklSxOuftl8E1k62 zerHO/wbjdHWIQlF5PQQNHLqWPHyyLMIACDoDJmMvLpZTHflVsv9vKoYcZ3+bpxlumsw WliNrd5PkFwvEUwJTbLpg4UXx5dQRa+9+sQ7vTshU+0ti4x5DDXZqGY6rMnjJYZqhaxa u2f5EaNp/FaCtBHiqdYUGGJC0SCvDuXO1dYJSuC5yx1k/srJ4GJp2lqrN84xbggD9Kkj a3giNcKZBulFsd97d3kqeK+OiGVE1nabAqYrI3PMsB2Ok8gMYv1/zm2cqnBbg9+7CZK1 nuBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date:dmarc-filter:arc-authentication-results; bh=gQ+bSdzrHsgZ0tPvjjsHpc9TV5ndIQvweVeCeN75T3Y=; b=Y+k77xtt7PMxnnJrQbLhVC+7lktm15KxlKKjA+2hTtlaF6K69ypvcomEo6HZYF5puI lF/lhGL3jOYPBiclvp4n0B9JHSakAvlTe0dUj1e30fKU05uhpZB3HkRt799j5MbI5r3b Ac9WMnQMtITb4FkaJqIp++NcmisR8n1b0oqNQUmhTkRnCrhVZhDCRXhfMRgbiL4l3XMs iYHbTbUpRhg/a9d4JaU5Bu2NznFQfIs9jacAepIC8lomEVI2i9YEm01wuDErrY31RWe7 qRr9g+DHWD/p39bqyFpkZQfhVR+k6HrO919iWElbfckL5k+WxhkoNXq8n+VIPgnLOikR 1S6A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l18si5814247pgn.103.2018.02.26.10.10.36; Mon, 26 Feb 2018 10:10:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751946AbeBZSJE (ORCPT + 99 others); Mon, 26 Feb 2018 13:09:04 -0500 Received: from mail.kernel.org ([198.145.29.99]:49710 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751697AbeBZSJD (ORCPT ); Mon, 26 Feb 2018 13:09:03 -0500 Received: from localhost (unknown [69.55.156.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 9319C2075D; Mon, 26 Feb 2018 18:09:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9319C2075D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=helgaas@kernel.org Date: Mon, 26 Feb 2018 12:09:01 -0600 From: Bjorn Helgaas To: Lorenzo Pieralisi Cc: Niklas Cassel , kishon@ti.com, Arnd Bergmann , Greg Kroah-Hartman , Niklas Cassel , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 2/3] misc: pci_endpoint_test: Handle 64-bit BARs properly Message-ID: <20180226180901.GB25159@bhelgaas-glaptop.roam.corp.google.com> References: <20180208123346.20784-1-niklas.cassel@axis.com> <20180208123346.20784-3-niklas.cassel@axis.com> <20180226172618.GA26815@e107981-ln.cambridge.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180226172618.GA26815@e107981-ln.cambridge.arm.com> User-Agent: Mutt/1.9.2 (2017-12-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Feb 26, 2018 at 05:26:18PM +0000, Lorenzo Pieralisi wrote: > On Thu, Feb 08, 2018 at 01:33:45PM +0100, Niklas Cassel wrote: > > A 64-bit BAR uses the succeeding BAR for the upper bits, > > so we cannot simply call pci_ioremap_bar() on every single BAR. > > > > Ignore BARs that does not have a valid resource length. > > > > pci 0000:01:00.0: BAR 4: assigned [mem 0xc0300000-0xc031ffff 64bit] > > pci 0000:01:00.0: BAR 2: assigned [mem 0xc0320000-0xc03203ff 64bit] > > pci 0000:01:00.0: BAR 0: assigned [mem 0xc0320400-0xc03204ff 64bit] > > pci-endpoint-test 0000:01:00.0: can't ioremap BAR 1: [??? 0x00000000 flags 0x0] > > pci-endpoint-test 0000:01:00.0: failed to read BAR1 > > pci-endpoint-test 0000:01:00.0: can't ioremap BAR 3: [??? 0x00000000 flags 0x0] > > pci-endpoint-test 0000:01:00.0: failed to read BAR3 > > pci-endpoint-test 0000:01:00.0: can't ioremap BAR 5: [??? 0x00000000 flags 0x0] > > pci-endpoint-test 0000:01:00.0: failed to read BAR5 > > > > Signed-off-by: Niklas Cassel > > --- > > Lorenzo/Bjorn: pci_resource_len() seems to fix my problem, > > but is it the correct function to use here? > > If BAR[x] is a 64-bit BAR, I'm assuming that pci_resource_len() on BAR[x+1] > > will always return 0 (since BAR[x+1] cannot have any prefetchable/type bits > > when BAR[x] is 64-bit). > > > > drivers/misc/pci_endpoint_test.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c > > index 320276f42653..3af31bfdcfdd 100644 > > --- a/drivers/misc/pci_endpoint_test.c > > +++ b/drivers/misc/pci_endpoint_test.c > > @@ -534,6 +534,8 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev, > > } > > > > for (bar = BAR_0; bar <= BAR_5; bar++) { > > + if (pci_resource_len(pdev, bar) == 0) > > + continue; > > Should not it be handled by checking the resource flags as you loop > through the bar counter and incrementing the bar counter (+1) if > IORESOURCE_MEM_64 is detected ? I agree, pci_resource_len() is the wrong thing here. The length (actually the entire resource[x]) *should* be zero if the slot corresponds to the upper bits of a 64-bit BAR, but I think it would be more natural to do this: if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) base = pci_ioremap_bar(pdev, bar); You *could* check for IORESOURCE_MEM_64 and increment "bar" if you find it, but I don't think that's really idiomatic, and it builds in a little bit of unnecessary knowledge about how the PCI core maps BAR registers to the resource[] array. > > base = pci_ioremap_bar(pdev, bar); > > if (!base) { > > dev_err(dev, "failed to read BAR%d\n", bar); > > -- > > 2.14.2 > >