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Subject: Re: [PATCH v3] KVM: X86: Allow userspace to define the microcode
 version
From:   Nadav Amit <nadav.amit@gmail.com>
In-Reply-To: <1519694331-16368-1-git-send-email-wanpengli@tencent.com>
Date:   Mon, 26 Feb 2018 17:30:59 -0800
Cc:     linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
        Paolo Bonzini <pbonzini@redhat.com>,
        =?utf-8?B?UmFkaW0gS3LEjW3DocWZ?= <rkrcmar@redhat.com>,
        Liran Alon <liran.alon@oracle.com>
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References: <1519694331-16368-1-git-send-email-wanpengli@tencent.com>
To:     Wanpeng Li <kernellwp@gmail.com>
Sender: linux-kernel-owner@vger.kernel.org
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Wanpeng Li <kernellwp@gmail.com> wrote:

> From: Wanpeng Li <wanpengli@tencent.com>
>=20
> Linux (among the others) has checks to make sure that certain features=20=

> aren't enabled on a certain family/model/stepping if the microcode =
version=20
> isn't greater than or equal to a known good version.
>=20
> By exposing the real microcode version, we're preventing buggy guests =
that
> don't check that they are running virtualized (i.e., they should trust =
the
> hypervisor) from disabling features that are effectively not buggy.
>=20
> Suggested-by: Filippo Sironi <sironi@amazon.de>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Radim Kr=C4=8Dm=C3=A1=C5=99 <rkrcmar@redhat.com>
> Cc: Liran Alon <liran.alon@oracle.com>
> Signed-off-by: Wanpeng Li <wanpengli@tencent.com>
> ---
> v2 -> v3:
> * remove the shifts
> * add the MSR_IA32_UCODE_REV version to the "feature MSRs"
> v1 -> v2:
> * add MSR_IA32_UCODE_REV to emulated_msrs
>=20
> arch/x86/include/asm/kvm_host.h |  1 +
> arch/x86/kvm/x86.c              | 19 +++++++++++++++----
> 2 files changed, 16 insertions(+), 4 deletions(-)
>=20
> diff --git a/arch/x86/include/asm/kvm_host.h =
b/arch/x86/include/asm/kvm_host.h
> index 938d453..6e13f2f 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -507,6 +507,7 @@ struct kvm_vcpu_arch {
> 	u64 smi_count;
> 	bool tpr_access_reporting;
> 	u64 ia32_xss;
> +	u32 microcode_version;
>=20
> 	/*
> 	 * Paging state of the vcpu
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index d4985a9..00af28e 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -1058,6 +1058,7 @@ static unsigned num_emulated_msrs;
> static u32 msr_based_features[] =3D {
> 	MSR_IA32_ARCH_CAPABILITIES,
> 	MSR_F10H_DECFG,
> +	MSR_IA32_UCODE_REV,
> };
>=20
> static unsigned int num_msr_based_features;
> @@ -1067,8 +1068,14 @@ static int do_get_msr_feature(struct kvm_vcpu =
*vcpu, unsigned index, u64 *data)
> 	struct kvm_msr_entry msr;
>=20
> 	msr.index =3D index;
> -	if (kvm_x86_ops->get_msr_feature(&msr))
> -		return 1;
> +	switch (msr.index) {
> +	case MSR_IA32_UCODE_REV:
> +		rdmsrl(msr.index, msr.data);
> +		break;
> +	default:
> +		if (kvm_x86_ops->get_msr_feature(&msr))
> +			return 1;
> +	}
>=20
> 	*data =3D msr.data;
>=20
> @@ -2248,7 +2255,6 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, =
struct msr_data *msr_info)
>=20
> 	switch (msr) {
> 	case MSR_AMD64_NB_CFG:
> -	case MSR_IA32_UCODE_REV:
> 	case MSR_IA32_UCODE_WRITE:
> 	case MSR_VM_HSAVE_PA:
> 	case MSR_AMD64_PATCH_LOADER:
> @@ -2256,6 +2262,10 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, =
struct msr_data *msr_info)
> 	case MSR_AMD64_DC_CFG:
> 		break;
>=20
> +	case MSR_IA32_UCODE_REV:
> +		if (msr_info->host_initiated)
> +			vcpu->arch.microcode_version =3D data;
> +		break;
> 	case MSR_EFER:
> 		return set_efer(vcpu, data);
> 	case MSR_K7_HWCR:
> @@ -2551,7 +2561,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, =
struct msr_data *msr_info)
> 		msr_info->data =3D 0;
> 		break;
> 	case MSR_IA32_UCODE_REV:
> -		msr_info->data =3D 0x100000000ULL;
> +		msr_info->data =3D (u64)vcpu->arch.microcode_version;

I think that the shifts are missing here (the version should be on the =
high
bits according to intel_get_microcode_revision() ).