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Date:   Mon, 26 Feb 2018 18:11:45 -0800
From:   skannan@codeaurora.org
To:     Mark Rutland <mark.rutland@arm.com>
Cc:     Peter Zijlstra <peterz@infradead.org>,
        Ingo Molnar <mingo@redhat.com>,
        Arnaldo Carvalho de Melo <acme@kernel.org>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Jiri Olsa <jolsa@redhat.com>,
        Namhyung Kim <namhyung@kernel.org>, avilaj@codeaurora.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 2/2] perf/core: Add support for PMUs that can be read
 from any CPU
In-Reply-To: <20180225143802.denbkubqjg2dc7af@salmiak>
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 <20180225143802.denbkubqjg2dc7af@salmiak>
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On 2018-02-25 06:38, Mark Rutland wrote:
> On Fri, Feb 23, 2018 at 04:19:38PM -0800, Saravana Kannan wrote:
>> Some PMUs events can be read from any CPU. So allow the PMU to mark
>> events as such. For these events, we don't need to reject reads or
>> make smp calls to the event's CPU and cause unnecessary wake ups.
>> 
>> Good examples of such events would be events from caches shared across
>> all CPUs.
> 
> I think that if we need to generalize PERF_EV_CAP_READ_ACTIVE_PKG, it 
> would be
> better to give events a pointer to a cpumask. That could then cover all 
> cases
> quite trivially:
> 
> static int __perf_event_read_cpu(struct perf_event *event, int 
> event_cpu)
> {
> 	int local_cpu = smp_processor_id();
> 
> 	if (event->read_mask &&
> 	    cpumask_test_cpu(local_cpu, event->read_mask))
> 		event_cpu = local_cpu;
> 
> 	return event_cpu;
> }
> 

This is a good improvement on my attempt. If I send a patch for this, is 
that something you'd be willing to incorporate into your patch set and 
make sure the DSU pmu driver handles it correctly?

> ... in the PERF_EV_CAP_READ_ACTIVE_PKG case, we can use the exiting(?) 
> package
> masks, and more generally we can re-use the PMU's affinit mask if it 
> has one.
> 
> That said, I see that many pmu::read() implementations have 
> side-effects on
> hwc->prev_count, and event->count, so I worry that this won't be sfe in 
> general
> (e.g. if we race with the IRQ handler on another CPU).
> 

Yeah, this doesn't have to be mandatory. It can be an optional mask the 
PMU can set up during perf event init.

Peter,

Is this something that's acceptable to you?

Thanks,
Saravana