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[209.132.180.67]) by mx.google.com with ESMTP id d5si6526737pgn.832.2018.02.26.21.56.18; Mon, 26 Feb 2018 21:56:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=kJ+85+wC; dkim=pass header.i=@codeaurora.org header.s=default header.b=WNUky4yf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751937AbeB0FzS (ORCPT + 99 others); Tue, 27 Feb 2018 00:55:18 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:50926 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751656AbeB0FzO (ORCPT ); Tue, 27 Feb 2018 00:55:14 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 4E18960848; Tue, 27 Feb 2018 05:55:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1519710914; bh=Sy5try8QpMAIcvM3gkD4cFQ/1cEAO1YYvvqhBXvIXaQ=; h=From:To:Cc:Subject:Date:From; b=kJ+85+wCDmnxNKQUJAaZ7W2rpy21ymLq9FQGXjmf5eEYX6E47COBUBx0GvGqqcdKb JVvGEdSYUUdLp5mMNrKBMJjDj5ZvjCXGHY1k1vz2qDLEFcpvrnD+qjp+NquTdW1Bdt 7Sv3oMmn2GVxLBT1GZgOQ/FrMJAVAU68CO+I8NVc= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from CANG02.ap.qualcomm.com (unknown [180.166.53.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: cang@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1603260285; Tue, 27 Feb 2018 05:55:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1519710913; bh=Sy5try8QpMAIcvM3gkD4cFQ/1cEAO1YYvvqhBXvIXaQ=; h=From:To:Cc:Subject:Date:From; b=WNUky4yfmHqEMvLHVuOt2YYTqP73gZzKO53OusJk4C6DMvh6vNg8jwI0Oe419JffE DF4Cd9uqPgRhlwRrcq0Kjx64ytEr/wdOgZv5Yf3vicZAfFZmAkZ0uKXr6AZTSz7b+N tV0zSnyNE1/9Kx79+rrz6j9KC37Gj8gX50TWVszo= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1603260285 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=cang@codeaurora.org From: Can Guo To: subhashj@codeaurora.org, asutoshd@codeaurora.org, vivek.gautam@codeaurora.org, rnayak@codeaurora.org, vinholikatti@gmail.com, jejb@linux.vnet.ibm.com, martin.petersen@oracle.com Cc: linux-scsi@vger.kernel.org, Gilad Broner , Can Guo , Rob Herring , Mark Rutland , Venkat Gopalakrishnan , Yaniv Gardi , Sujit Reddy Thumma , Amit Nischal , Maya Erez , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2] scsi: ufs-qcom: add number of lanes for Tx and Rx links Date: Tue, 27 Feb 2018 13:46:17 +0800 Message-Id: <20180227055500.10416-1-cang@codeaurora.org> X-Mailer: git-send-email 2.15.0.windows.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Gilad Broner Different platforms may have different number of lanes for the UFS Tx/Rx links. Add parameter to device tree specifying how many lanes should be configured for the UFS Tx/Rx links. And don't print err message for clocks that are optional, this leads to unnecessary confusion about failure. Signed-off-by: Gilad Broner Signed-off-by: Subhash Jadavani Signed-off-by: Can Guo --- Changes since v1: - Change commit subject for better description. - Incorporated Rob's review comments to use lanes-tx and lanes-rx to handle asymmetric Tx/Rx links. .../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 4 ++ drivers/scsi/ufs/ufs-qcom.c | 65 +++++++++++++--------- drivers/scsi/ufs/ufshcd.c | 29 ++++++++++ drivers/scsi/ufs/ufshcd.h | 5 ++ 4 files changed, 78 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt index 5357919..257308e 100644 --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt +++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt @@ -31,6 +31,10 @@ Optional properties: defined or a value in the array is "0" then it is assumed that the frequency is set by the parent clock or a fixed rate clock source. +- lanes-tx : Number of lanes available for Tx direction - either 1 or 2. + If not specified, default is 2 lanes. +- lanes-rx : Number of lanes available for Rx direction - either 1 or 2. + If not specified, default is 2 lanes. Note: If above properties are not defined it can be assumed that the supply regulators or clocks are always on. diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c index 4cdffa4..154e7f1 100644 --- a/drivers/scsi/ufs/ufs-qcom.c +++ b/drivers/scsi/ufs/ufs-qcom.c @@ -50,13 +50,10 @@ static int ufs_qcom_host_clk_get(struct device *dev, int err = 0; clk = devm_clk_get(dev, name); - if (IS_ERR(clk)) { + if (IS_ERR(clk)) err = PTR_ERR(clk); - dev_err(dev, "%s: failed to get %s err %d", - __func__, name, err); - } else { + else *clk_out = clk; - } return err; } @@ -78,9 +75,11 @@ static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) if (!host->is_lane_clks_enabled) return; - clk_disable_unprepare(host->tx_l1_sync_clk); + if (host->tx_l1_sync_clk) + clk_disable_unprepare(host->tx_l1_sync_clk); clk_disable_unprepare(host->tx_l0_sync_clk); - clk_disable_unprepare(host->rx_l1_sync_clk); + if (host->rx_l1_sync_clk) + clk_disable_unprepare(host->rx_l1_sync_clk); clk_disable_unprepare(host->rx_l0_sync_clk); host->is_lane_clks_enabled = false; @@ -104,21 +103,23 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) if (err) goto disable_rx_l0; - err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk", - host->rx_l1_sync_clk); - if (err) - goto disable_tx_l0; + if (host->hba->lanes_rx > 1) { + err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk", + host->rx_l1_sync_clk); + if (err) + goto disable_tx_l0; + } - err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk", - host->tx_l1_sync_clk); - if (err) - goto disable_rx_l1; + if (host->hba->lanes_tx > 1) { + /* The tx lane1 clk could be muxed, hence keep this optional */ + if (host->tx_l1_sync_clk) + ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk", + host->tx_l1_sync_clk); + } host->is_lane_clks_enabled = true; goto out; -disable_rx_l1: - clk_disable_unprepare(host->rx_l1_sync_clk); disable_tx_l0: clk_disable_unprepare(host->tx_l0_sync_clk); disable_rx_l0: @@ -134,21 +135,35 @@ static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk", &host->rx_l0_sync_clk); - if (err) + if (err) { + dev_err(dev, "%s: failed to get rx_lane0_sync_clk, err %d", + __func__, err); goto out; + } err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk", &host->tx_l0_sync_clk); - if (err) + if (err) { + dev_err(dev, "%s: failed to get tx_lane0_sync_clk, err %d", + __func__, err); goto out; + } - err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk", - &host->rx_l1_sync_clk); - if (err) - goto out; + if (host->hba->lanes_rx > 1) { + err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk", + &host->rx_l1_sync_clk); + if (err) { + dev_err(dev, "%s: failed to get rx_lane1_sync_clk, err %d", + __func__, err); + goto out; + } + } - err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk", - &host->tx_l1_sync_clk); + if (host->hba->lanes_tx > 1) { + /* The tx lane1 clk could be muxed, hence keep this optional */ + ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk", + &host->tx_l1_sync_clk); + } out: return err; } diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index b0ade73..307d0070 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -39,6 +39,7 @@ #include #include +#include #include "ufshcd.h" #include "unipro.h" @@ -74,6 +75,8 @@ /* Interrupt aggregation default timeout, unit: 40us */ #define INT_AGGR_DEF_TO 0x02 +#define UFSHCD_DEFAULT_LANES_PER_DIRECTION 2 + #define ufshcd_toggle_vreg(_dev, _vreg, _on) \ ({ \ int _ret; \ @@ -5530,6 +5533,30 @@ static struct devfreq_dev_profile ufs_devfreq_profile = { .get_dev_status = ufshcd_devfreq_get_dev_status, }; +static void ufshcd_init_lanes_per_dir(struct ufs_hba *hba) +{ + struct device *dev = hba->dev; + int ret; + + ret = of_property_read_u32(dev->of_node, "lanes-tx", + &hba->lanes_tx); + if (ret) { + dev_dbg(hba->dev, + "%s: failed to read lanes-tx, ret=%d\n", + __func__, ret); + hba->lanes_tx = UFSHCD_DEFAULT_LANES_PER_DIRECTION; + } + + ret = of_property_read_u32(dev->of_node, "lanes-rx", + &hba->lanes_rx); + if (ret) { + dev_dbg(hba->dev, + "%s: failed to read lanes-rx, ret=%d\n", + __func__, ret); + hba->lanes_rx = UFSHCD_DEFAULT_LANES_PER_DIRECTION; + } +} + /** * ufshcd_init - Driver initialization routine * @hba: per-adapter instance @@ -5553,6 +5580,8 @@ int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) hba->mmio_base = mmio_base; hba->irq = irq; + ufshcd_init_lanes_per_dir(hba); + err = ufshcd_hba_init(hba); if (err) goto out_error; diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index c40a0e7..b3b8abe 100644 --- a/drivers/scsi/ufs/ufshcd.h +++ b/drivers/scsi/ufs/ufshcd.h @@ -500,6 +500,11 @@ struct ufs_hba { bool wlun_dev_clr_ua; + /* Number of lanes available (1 or 2) for Tx */ + u32 lanes_tx; + /* Number of lanes available (1 or 2) for Rx */ + u32 lanes_rx; + struct ufs_pa_layer_attr pwr_info; struct ufs_pwr_mode_info max_pwr_info; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project