Received: by 10.223.185.116 with SMTP id b49csp5726102wrg; Tue, 27 Feb 2018 19:59:01 -0800 (PST) X-Google-Smtp-Source: AH8x225JQyF0uR0cNc/D6FaL2fG8Z5EocWFMqqO4yy7R9s8/pemkWR/oSBWV4HcRGErOBKsTkXL5 X-Received: by 10.99.117.24 with SMTP id q24mr12948186pgc.53.1519790340955; Tue, 27 Feb 2018 19:59:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519790340; cv=none; d=google.com; s=arc-20160816; b=tGp5+1EvWCWA5r1GR+Q5OD3tJkE/BYWXEc2I86rd7wK+OmYuYwNHilIiTrp46I9j9m iecLkOZs8jNbkCG64JxVstdM0gYU3WVyavf5GRKE+Ze2fXDcJ9ERuL7XyAL7IfY4Sm8m d7QSyBk3upZJV3uv5jt1GHZ3lRMMhWCsBDqq2lrO9x0c6OvdJCjrI/g+D4GwcG1E9PY+ xkpVol2xEujPzzWl6imH9usVH4+Cf1xZVT4IZ9OZ0ZxlpOI8ShdVrgDAxQxuncMSxUlA FiHor92aK54Pq64KYFMI+PHBENhrc2y9Id4nY2WvT/UoS3AttAeRvSYBLXYG7EtQKeM+ j/zg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=JlI9DP1HlKjji9zn/7bpfmOr/uB1krsnDWBdsArXfLk=; b=X21xleGKICkey9YRq+w//tWaUi7lPcGUwDa3Z6UtYlghhgOn5gzg5V5D0gDl/GRWcn jvMihX3SjRmwSDFCrQS8lgJNk00DxN71Wu17DKjPos+lG4YSYkpy2wT9Nsk9zH1NGmgr X2veNL9+GT0erpZ8d2HYXTkGSC6sSxbhi5OTEE6R+WJBaUYS6ogUNaQFYQdsYmfZqoqu UFH8zT+SWnkCHOj6DBQCsLMdhpQWoMXWSgGUPQwLgZRd3mnoBxzP+7OuWI7JMI3USf6V t6FRtRn7UmELPV/rSYcHNylPh0vfuiCA2cYfU7+Wqjpx+tsbUvGk4uSSIC3erAZu6lzI Yycg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RQH5Gop9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b89-v6si569970plb.809.2018.02.27.19.58.35; Tue, 27 Feb 2018 19:59:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RQH5Gop9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751930AbeB1D5q (ORCPT + 99 others); Tue, 27 Feb 2018 22:57:46 -0500 Received: from mail-pl0-f66.google.com ([209.85.160.66]:46115 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751811AbeB1D5o (ORCPT ); Tue, 27 Feb 2018 22:57:44 -0500 Received: by mail-pl0-f66.google.com with SMTP id y8-v6so757754pll.13 for ; Tue, 27 Feb 2018 19:57:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JlI9DP1HlKjji9zn/7bpfmOr/uB1krsnDWBdsArXfLk=; b=RQH5Gop988mVavWcfYWliQXqF72jFL+LSV+W9ay8EmY3404fRDS+trv+19X3otPlGT iTus77JzCzC/3S4OPTrf4beE8/lW7yQJPSHh2EKyOVmP28dYgiYKPQeHR9zlOSl6O4TO N1xhBTeOrt5EmqDXYFrv4j/ht3cAz8hCX179E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JlI9DP1HlKjji9zn/7bpfmOr/uB1krsnDWBdsArXfLk=; b=e5DKAEfPpjxR48BXX3CIqigTIzX/HqH//8q4hh3HSOZmLZEDtUFmBnxxnZZG1yvsUo esNz5wPYQgXXZjtlrNLpLovQhyl8fs3XdpOLnENZyG9aI1/2UQeY4FOlme34BU6n6Xk2 gfEfroucT0ogec/mbdfwe5MkTZw7zKfHwbvDxOwuUVgSW9Y+H91T2aMjpTxJW8ofogS9 4InsSx+8b/tUY8tbhFeMhLeNOb9aQF6bVeLyLjJmGNVVkxNklXvC3SryKuXGGbQwpKd1 sw8H3NeHxwug1I6SwPkkb49fyiZ4V9XzMsdgW8aqOhHeZ6PXZiwx22AEh5WsjPG3oMk0 Pcxw== X-Gm-Message-State: APf1xPB+99VmCFRaF5SAhOx9ADg55mXpdsJxOg51n4ERmYfM/ywFg9b6 hOyWnTcAH0p5ZM42H0+2fTEFnQ== X-Received: by 2002:a17:902:7404:: with SMTP id g4-v6mr16383927pll.235.1519790263134; Tue, 27 Feb 2018 19:57:43 -0800 (PST) Received: from localhost.localdomain (176.122.172.82.16clouds.com. [176.122.172.82]) by smtp.gmail.com with ESMTPSA id q17sm739911pgt.7.2018.02.27.19.57.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Feb 2018 19:57:42 -0800 (PST) From: Alex Shi To: Marc Zyngier , Will Deacon , Ard Biesheuvel , Catalin Marinas , stable@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alex Shi Subject: [PATCH 02/29] arm64: mm: Move ASID from TTBR0 to TTBR1 Date: Wed, 28 Feb 2018 11:56:24 +0800 Message-Id: <1519790211-16582-3-git-send-email-alex.shi@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519790211-16582-1-git-send-email-alex.shi@linaro.org> References: <1519790211-16582-1-git-send-email-alex.shi@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Will Deacon commit 7655abb95386 upstream. In preparation for mapping kernelspace and userspace with different ASIDs, move the ASID to TTBR1 and update switch_mm to context-switch TTBR0 via an invalid mapping (the zero page). Reviewed-by: Mark Rutland Tested-by: Laura Abbott Tested-by: Shanker Donthineni Signed-off-by: Will Deacon Signed-off-by: Alex Shi Conflicts: no pre_ttbr0_update_workaround in arch/arm64/mm/proc.S --- arch/arm64/include/asm/mmu_context.h | 7 +++++++ arch/arm64/include/asm/pgtable-hwdef.h | 1 + arch/arm64/include/asm/proc-fns.h | 6 ------ arch/arm64/mm/proc.S | 9 ++++++--- 4 files changed, 14 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index a501853..b96c4799 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -50,6 +50,13 @@ static inline void cpu_set_reserved_ttbr0(void) isb(); } +static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm) +{ + BUG_ON(pgd == swapper_pg_dir); + cpu_set_reserved_ttbr0(); + cpu_do_switch_mm(virt_to_phys(pgd),mm); +} + /* * TCR.T0SZ value to use when the ID map is active. Usually equals * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index eb0c2bd..8df4cb6 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -272,6 +272,7 @@ #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT) #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT) +#define TCR_A1 (UL(1) << 22) #define TCR_ASID16 (UL(1) << 36) #define TCR_TBI0 (UL(1) << 37) #define TCR_HA (UL(1) << 39) diff --git a/arch/arm64/include/asm/proc-fns.h b/arch/arm64/include/asm/proc-fns.h index 14ad6e4..16cef2e 100644 --- a/arch/arm64/include/asm/proc-fns.h +++ b/arch/arm64/include/asm/proc-fns.h @@ -35,12 +35,6 @@ extern u64 cpu_do_resume(phys_addr_t ptr, u64 idmap_ttbr); #include -#define cpu_switch_mm(pgd,mm) \ -do { \ - BUG_ON(pgd == swapper_pg_dir); \ - cpu_do_switch_mm(virt_to_phys(pgd),mm); \ -} while (0) - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ #endif /* __ASM_PROCFNS_H */ diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 352c73b..3378f3e 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -132,9 +132,12 @@ ENDPROC(cpu_do_resume) * - pgd_phys - physical address of new TTB */ ENTRY(cpu_do_switch_mm) + mrs x2, ttbr1_el1 mmid x1, x1 // get mm->context.id - bfi x0, x1, #48, #16 // set the ASID - msr ttbr0_el1, x0 // set TTBR0 + bfi x2, x1, #48, #16 // set the ASID + msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set) + isb + msr ttbr0_el1, x0 // now update TTBR0 isb alternative_if ARM64_WORKAROUND_CAVIUM_27456 ic iallu @@ -222,7 +225,7 @@ ENTRY(__cpu_setup) * both user and kernel. */ ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ - TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 + TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | TCR_A1 tcr_set_idmap_t0sz x10, x9 /* -- 2.7.4