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[209.85.217.178]) by smtp.gmail.com with ESMTPSA id j26sm199363ual.5.2018.02.28.04.49.27 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Feb 2018 04:49:28 -0800 (PST) Received: by mail-ua0-f178.google.com with SMTP id f5so1429723uam.5 for ; Wed, 28 Feb 2018 04:49:27 -0800 (PST) X-Received: by 10.159.60.143 with SMTP id s15mr13403790uai.56.1519822167327; Wed, 28 Feb 2018 04:49:27 -0800 (PST) MIME-Version: 1.0 Received: by 10.176.0.99 with HTTP; Wed, 28 Feb 2018 04:49:06 -0800 (PST) In-Reply-To: References: <20180228111113.13639-1-jeffy.chen@rock-chips.com> From: Tomasz Figa Date: Wed, 28 Feb 2018 21:49:06 +0900 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] soc: rockchip: power-domain: remove PM clocks To: Geert Uytterhoeven Cc: Jeffy Chen , Linux Kernel Mailing List , Dmitry Torokhov , Robin Murphy , Heiko Stuebner , Caesar Wang , Elaine Zhang , "open list:ARM/Rockchip SoC..." , Geert Uytterhoeven , Linux ARM , Ulf Hansson Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Feb 28, 2018 at 9:32 PM, Geert Uytterhoeven wrote: > Hi Tomasz, > > On Wed, Feb 28, 2018 at 1:29 PM, Tomasz Figa wrote: >> On Wed, Feb 28, 2018 at 9:17 PM, Geert Uytterhoeven >> wrote: >>> On Wed, Feb 28, 2018 at 12:11 PM, Jeffy Chen wrote: >>>> Currently we are adding all of the attached devices' clocks as pm clocks >>>> and enable them when powering on the power domain. >>>> >>>> This seems unnecessary, because those clocks are already controlled in >>>> the devices' drivers with better error handling. >>>> >>>> Tested on my chromebook minnie(rk3288) and chromebook kevin(rk3399). >>>> >>>> Signed-off-by: Jeffy Chen >>> >>> Thanks for your patch! >>> >>> Just wondering: so you prefer to handle the clocks explicitly in all drivers, >>> instead of delegating this task to Runtime PM? >> >> Is it already possible to gate clocks immediately when the device >> idles, but defer turning the power domain off until time long enough >> to cover the power down and up latency elapses? > > I'm not 100% sure. > Note that clocks are turned off when the device idles, while powering down > the power domain requires all devices in the domain to be idle. I remember seeing some ongoing work for multiple power states of PM domains on LWN, which could possibly solve it. I guess it's not done yet. Also, for Rockchip SoC, the typical setup is one device per domain, +/- some auxiliary devices such as IOMMU, which would have the same runtime PM state as the master device. (It isn't implemented yet, but Jeffy posted patches for using device links some time ago.) > >> Also, how about systems where runtime PM is disabled? I think that's >> one of the reasons we control the clocks explicitly in the drivers >> anyway. > > On many platforms, Runtime PM is always enabled. Can we make such assumption? If so, could we just make an explicit "select PM_RUNTIME" in Kconfig of the SoC? Best regards, Tomasz