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[209.132.180.67]) by mx.google.com with ESMTP id 62-v6si1532329ple.491.2018.02.28.09.29.02; Wed, 28 Feb 2018 09:29:16 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=o5zVBAdy; dkim=pass header.i=@codeaurora.org header.s=default header.b=mS2qvlxU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933589AbeB1R1r (ORCPT + 99 others); Wed, 28 Feb 2018 12:27:47 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:36988 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932503AbeB1R1o (ORCPT ); Wed, 28 Feb 2018 12:27:44 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 34763602BA; Wed, 28 Feb 2018 17:27:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1519838864; bh=CUKciLEsQzR77+rn56hwY1WiZ6x7FFTXO1zCcL+meLg=; h=From:To:Cc:Subject:Date:From; b=o5zVBAdy+INRIfrsppKRfVQucJTelKSlEELQA58Q5iG/og8+Xwk1cqcogzN/Sm0fT bradR9ZTsjrCIPqM4bPwuiiTERZtPwv2XRqJfEc9iLdJbUcpcwIS0SwKAYrpcKS1yt CxzXCyR4zPSCtRqk4ZXp/xUnirCvUvKqi956HuZs= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E5AEF60240; Wed, 28 Feb 2018 17:27:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1519838863; bh=CUKciLEsQzR77+rn56hwY1WiZ6x7FFTXO1zCcL+meLg=; h=From:To:Cc:Subject:Date:From; b=mS2qvlxUcK3eyCqBAb+eMUENF7b23nsw/BeQKBFMbgKEZVcEbTdJq3nt1RCRinjNF I1UJwiQUO827iKci8wyvZBmIHUyidpezdoi88x+1Z51FsM2iN2jeWSkKdyXeeh+yAc 2nRU8869Kbha2ErEFzhltRecg03+lwuCtVuMhE0E= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E5AEF60240 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, asathyak@codeaurora.org, Lina Iyer Subject: [PATCH v8 0/2] irqchip: qcom: add support for PDC interrupt controller Date: Wed, 28 Feb 2018 10:27:28 -0700 Message-Id: <20180228172730.25022-1-ilina@codeaurora.org> X-Mailer: git-send-email 2.16.2 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Changes since v7: - fix whitespace alignment for multi-line statement - add Rob H 'reviewed-by' for DT bindings - rebase on top of 4.6-rc3 On newer Qualcomm Techonologies Inc's SoCs like the SDM845, the GIC is in a power domain that can be powered off when not needed. Interrupts that need to be sensed even when the GIC is powered off, are routed through an interrupt controller in an always-on domain called the Power Domain Controller a.k.a PDC. This series adds support for the PDC's interrupt controller. Please consider reviewing these patches. RFC v1: https://patchwork.kernel.org/patch/10180857/ RFC v2: https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1600634.html v3: https://lkml.org/lkml/2018/2/6/595 v4: https://www.spinics.net/lists/linux-arm-msm/msg32906.html v5: https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1605500.html v6: https://lkml.org/lkml/2018/2/9/545 v7: https://www.spinics.net/lists/kernel/msg2723942.html Lina Iyer (2): drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs dt-bindings/interrupt-controller: pdc: describe PDC device binding .../bindings/interrupt-controller/qcom,pdc.txt | 78 ++++++ drivers/irqchip/Kconfig | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/qcom-pdc.c | 311 +++++++++++++++++++++ 4 files changed, 399 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt create mode 100644 drivers/irqchip/qcom-pdc.c -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project