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From:   Bartosz Golaszewski <bgolaszewski@baylibre.com>
Date:   Thu, 1 Mar 2018 09:36:14 +0100
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Subject: Re: [PATCH v7 10/42] clk: davinci: New driver for davinci PSC clocks
To:     David Lechner <david@lechnology.com>
Cc:     linux-clk@vger.kernel.org,
        linux-devicetree <devicetree@vger.kernel.org>,
        arm-soc <linux-arm-kernel@lists.infradead.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@codeaurora.org>,
        Rob Herring <robh+dt@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Sekhar Nori <nsekhar@ti.com>,
        Kevin Hilman <khilman@kernel.org>,
        Adam Ford <aford173@gmail.com>,
        LKML <linux-kernel@vger.kernel.org>
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2018-02-28 22:40 GMT+01:00 David Lechner <david@lechnology.com>:
> On 02/28/2018 06:38 AM, Bartosz Golaszewski wrote:
>>
>>
>> I think I found the reason for the strange crashes we were
>> experiencing (emac core->name being NULL) thanks to Sekhar who pointed
>> me in the right direction.
>>
>> The mdio driver fails to probe with v7 due to the supplied clock rate
>> being wrong. Before failing we register the emac clock with
>> pm_clk_add_clk(). When clock_ops puts the clock, it decreases the
>> reference count of the clock, but we never actually increased it in
>> the first place in the line above. The core clock code then destroys
>> the associated clk_core structure. When the next user comes around (in
>> our case the clk debug functions) the system crashes.
>>
>> I believe there to be two issues: one is with v7 - we need to increase
>> the clock reference count in davinci_psc_genpd_attach_dev().
>>
>> Second is the error path in the clock framework - we should remove the
>> destroyed clk_core from the debug list, which is not being done now.
>>
>> Why we even need to track the refcount of clk_core is a mistery for me
>> though. Stephen, Mike?
>>
>> Best regards,
>> Bartosz Golaszewski
>
>
> Great find. I figured it had to be something like this, but I wasn't
> able to reproduce the problem yet.
>
> I suppose it is time to spin up a v8 with some fixes.

I still don't know why the mdio clock rate is much lower than in
mainline though. Any ideas?

Thanks,
Bart