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[209.132.180.67]) by mx.google.com with ESMTP id r6si2655148pfl.304.2018.03.01.00.56.07; Thu, 01 Mar 2018 00:56:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=uJ2DNC11; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965196AbeCAIdZ (ORCPT + 99 others); Thu, 1 Mar 2018 03:33:25 -0500 Received: from mail-qt0-f193.google.com ([209.85.216.193]:45044 "EHLO mail-qt0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964841AbeCAIdY (ORCPT ); Thu, 1 Mar 2018 03:33:24 -0500 Received: by mail-qt0-f193.google.com with SMTP id g60so6510571qtd.11 for ; Thu, 01 Mar 2018 00:33:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=hQvpfUyTGzMv23ArlZ828fXwGjUYB+MgOeU7NtcY45Q=; b=uJ2DNC11yTysptVYF5ZVBDCD3DTdNGBh39eEO/yW2ZeGAnH2eTsVPwXj1obOSALdOK 0xTv/1dy9wtwU+YzsqcBvA29AWjFjpcx9xmrrRBfMTyKrXtjWOxPUmVuy0HLNeuT0fi3 xEFQZKE+bgfSY1y/e8gi8shgSQ8jRCF7DJFG6Mnsw3kR36DQFtJy8kYHzJGwcaSQ0cnE XR7buV+qooHK5Jkk9GE1ck9radjiFoCkfGu3gzAI2YrwRYxzEe6VCZa0hCe0n/Tsr4nW gzcngnACSXGqpihuET4Lp6wcz8TcB13Iy9cegLEnzcsBrrFZIMBZi8lG97e1NfuDtU+N zjxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=hQvpfUyTGzMv23ArlZ828fXwGjUYB+MgOeU7NtcY45Q=; b=Rww4sG/egTd7KWzCLJRpb81Hd8L9OT16qq/52qTHcSbHgaUDqsIADyMF2JuACc8jJG DOMiTScHJ94uwBPzfVDTQBl6b6wdfEbvi7WVFUh5Hfw9Px9MD+i2o0utoB7t4GlFTMqM F48lDqxvR1ULCU+oTBPR9i/SjWxmruqF75TZR7nZEDZvdBR+CKH12eM+AM9VYNK0nOu5 3EjqBOLGa0h5G2oKuFIduU+NP8jY+WMAhohvzgFP5+L9BvPs3uDXXQR9Tagr8f2nu7uM 0UXfjEPdD3U6UY4uYlEyZMWEOq1gS/lFMxPLjPMYZZ42Yh3gQ6sjA3PoBj6mrftNevOv N1Eg== X-Gm-Message-State: AElRT7EtsdrGgqRwemExHHy8rMrTmrOWVuGlXh+AyFYQzo0/LoREea9m PbeDaqeStROp/9NYj+8Wv+MrPXsWiyQwyqckdTA= X-Received: by 10.200.28.8 with SMTP id a8mr1748732qtk.280.1519893203393; Thu, 01 Mar 2018 00:33:23 -0800 (PST) MIME-Version: 1.0 Received: by 10.200.47.219 with HTTP; Thu, 1 Mar 2018 00:33:22 -0800 (PST) In-Reply-To: <5A977638.8010506@rock-chips.com> References: <20180228111113.13639-1-jeffy.chen@rock-chips.com> <5A977638.8010506@rock-chips.com> From: Geert Uytterhoeven Date: Thu, 1 Mar 2018 09:33:22 +0100 X-Google-Sender-Auth: dOIuCGn5hVjePbx296WYZzz0aBs Message-ID: Subject: Re: [PATCH] soc: rockchip: power-domain: remove PM clocks To: JeffyChen Cc: Tomasz Figa , Linux Kernel Mailing List , Dmitry Torokhov , Robin Murphy , Heiko Stuebner , Caesar Wang , Elaine Zhang , "open list:ARM/Rockchip SoC..." , Geert Uytterhoeven , Linux ARM , Ulf Hansson Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jeffy, On Thu, Mar 1, 2018 at 4:40 AM, JeffyChen wrote: > if i'm reading the code right, the PM clk means: > 1/ the clocks which would be enabled while power on > 2/ these clocks are optional, it's ok if anything wrong with them > 3/ controlled by pm_domain(or USE_PM_CLK_RUNTIME_OPS & pm_clk_add_notifier) > > and currently we're adding all clocks of the attached device as PM clk in > rockchip PM domain driver, which seems wrong. because we might have these > kinds of clocks: > 1/ critical, should block power on if anything wrong with it(failed to get/ > prepare/ enable) > 2/ optional, could ignore it if anything wrong > 3/ only required in some special cases, for example register r/w, and > doesn't need to stay enabled while power on > > so maybe we can: > 1/ let the device(dts) or driver decide which clock is PM clk, and add it > using *pm_clk_add* APIs (even of_pm_clk_add_clks() if all clocks are pm clk) > > 2/ add support for critical PM clk, which would return error to the driver > if anything wrong > > 3/ make sure PM clk always be controlled(otherwise it might be unexpected > disabled by other clocks under the same clk parent?): > a) make sure Runtime PM is always enabled. and as discussed, we can select > PM in ARCH_ROCKCHIP On Renesas SoCs, we only add the device's module clock with pm_clk_add(). Drivers that don't care about properties of the module clock just call pm_runtime_*(). That way the same driver works on different SoCs using the same device, with and without power and/or clock domains. Drivers that care about properties of the module clock (mainly frequency) can still use the clk_*() API for that. Other (optional) clocks must be handled by the device driver itself. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds