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Date:   Thu, 1 Mar 2018 10:26:46 +0100
From:   Maxime Ripard <maxime.ripard@bootlin.com>
To:     =?utf-8?B?QW5kcsOp?= Przywara <andre.przywara@arm.com>
Cc:     hao5781286@gmail.com, thierry.reding@gmail.com, robh+dt@kernel.org,
        mark.rutland@arm.com, linux@armlinux.org.uk, wens@csie.org,
        Claudiu.Beznea@microchip.com, linux-gpio@vger.kernel.org,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org,
        linux-sunxi@googlegroups.com
Subject: Re: [linux-sunxi] [PATCH v2 1/4] dt-bindings: pwm: binding allwinner
 sun8i.
Message-ID: <20180301092646.44rxuwui2ssiar4u@flea>
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 <56645bca-9f4a-3191-72d8-32b60ebbc26e@arm.com>
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Hi,

On Wed, Feb 28, 2018 at 01:51:59AM +0000, Andr=E9 Przywara wrote:
> On 25/02/18 13:50, hao_zhang wrote:
> > This patch adds allwinner sun8i pwm binding documents.
> >=20
> > Signed-off-by: hao_zhang <hao5781286@gmail.com>
> > ---
> >  Documentation/devicetree/bindings/pwm/pwm-sun8i.txt | 18 +++++++++++++=
+++++
> >  1 file changed, 18 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sun8i.txt
> >=20
> > diff --git a/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt b/Docu=
mentation/devicetree/bindings/pwm/pwm-sun8i.txt
> > new file mode 100644
> > index 0000000..e8c48be
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt
> > @@ -0,0 +1,18 @@
> > +Allwinner sun8i R40/V40/T3 SoC PWM controller
> > +
> > +Required properties:
> > +  - compatible: should be one of:
> > +    - "allwinner,sun8i-r40-pwm"
> > +  - reg: physical base address and length of the controller's registers
> > +  - #pwm-cells: should be 3. See pwm.txt in this directory for a descr=
iption of
> > +    the cells format.
> > +  - clocks: From common clock binding, handle to the parent clock.
>=20
> The manual tells me that there are two possible clock sources (24 MHz
> OSC and APB1), with actually two bits for encoding the mux source,
> allowing for two more potential clock sources.
> So can we extend this description to provide up to four clocks, with a
> clock-names property telling the driver how this maps to the mux value?
> Either we use clock names matching the clocks mentioned in the manual:
> 	clocks =3D <&osc24M>, <&ccu CLK_APB1>;
> 	clock-names =3D "osc", "apb1";
> or we encode the mux values in the clock-names:
> 	clock-names =3D "mux-0", "mux-1";

I'd prefer the former.

> Don't know what's more widely used in those cases, the latter seems to
> be more future-proof.

Not really, nothing prevents the next generation to have three bits,
or even 32 bits to do the muxing :)

Maxime

--=20
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

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