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[209.132.180.67]) by mx.google.com with ESMTP id o14-v6si2819964pli.572.2018.03.01.02.19.38; Thu, 01 Mar 2018 02:19:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=k0x/tXO5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935833AbeCAKSl (ORCPT + 99 others); Thu, 1 Mar 2018 05:18:41 -0500 Received: from mail-it0-f50.google.com ([209.85.214.50]:51517 "EHLO mail-it0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935717AbeCAKSM (ORCPT ); Thu, 1 Mar 2018 05:18:12 -0500 Received: by mail-it0-f50.google.com with SMTP id u66so4719617ith.1 for ; Thu, 01 Mar 2018 02:18:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=FAZXJ1gWKHNPr1HZsykwds7v+UPCcHLpH1Z+VyQTtdU=; b=k0x/tXO50WesRVG+6HxW3apvU0T/WkDRwZajsI4+H3OWW7rerdVJKNmLKrUB2daxLP tFLq0keEhkKykeY6dJaaiNnRiK8ji0kq150TAYibDINDau9tXTRfvqGmHoMEsB3us/RR Gzf6uReFJc3HnmHHEnuBB2Wd32tDQU8Wxzu3Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=FAZXJ1gWKHNPr1HZsykwds7v+UPCcHLpH1Z+VyQTtdU=; b=B7vDOBopfdG0HeUmD56cF8L5xTm2ptl8lpbDLkEnjMaeS43EOt6COn3IuhID/JdXgq 7YRPOEzEahw1upnYiPkegxPNTZ270vZnaJsgq0LwSasdDEMpkXUxYrnzbeTM19DyQr33 Zikvhx6VR3RDh7YC2Tg4MZeaHBjEq6tr4edpMhhQYN+lfb1KIL5Hr/q9Etr3K8/mb14K YR4plEx9hxG1CWiiX1G+go4stg4isL0G26LG74YH4+nGvY9llTiW16DotEGxOhFDxIV5 Qu1ghiT2ANGpYyEgoyOK9IAnM2skOmCtQhXIgTCFTwX3McDQORIbt1iByqtIlt1Nv7D6 gdTw== X-Gm-Message-State: APf1xPCuIsuR7AHpJ4Gi34KyDhlhWy9pDoAzcrOJxS6HcsMpnl0a5YL5 N+DvjGwHJbGenUDS2SMKcP+cXBwYSAfA0F59uufhCQ== X-Received: by 10.36.73.95 with SMTP id z92mr2040985ita.38.1519899490705; Thu, 01 Mar 2018 02:18:10 -0800 (PST) MIME-Version: 1.0 Received: by 10.2.91.10 with HTTP; Thu, 1 Mar 2018 02:18:10 -0800 (PST) In-Reply-To: References: <20180228111113.13639-1-jeffy.chen@rock-chips.com> <5A977638.8010506@rock-chips.com> From: Ulf Hansson Date: Thu, 1 Mar 2018 11:18:10 +0100 Message-ID: Subject: Re: [PATCH] soc: rockchip: power-domain: remove PM clocks To: Geert Uytterhoeven , JeffyChen , Tomasz Figa Cc: Linux Kernel Mailing List , Dmitry Torokhov , Robin Murphy , Heiko Stuebner , Caesar Wang , Elaine Zhang , "open list:ARM/Rockchip SoC..." , Geert Uytterhoeven , Linux ARM , Linux PM Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org +linux-pm Geert, Jeffry, Tomasz, Apologize for side-tracking the discussion. Just wanted to add a few comments, whatever it's worth to you. On 1 March 2018 at 09:33, Geert Uytterhoeven wrote: > Hi Jeffy, > > On Thu, Mar 1, 2018 at 4:40 AM, JeffyChen wrote: >> if i'm reading the code right, the PM clk means: >> 1/ the clocks which would be enabled while power on >> 2/ these clocks are optional, it's ok if anything wrong with them >> 3/ controlled by pm_domain(or USE_PM_CLK_RUNTIME_OPS & pm_clk_add_notifier) >> >> and currently we're adding all clocks of the attached device as PM clk in >> rockchip PM domain driver, which seems wrong. because we might have these >> kinds of clocks: >> 1/ critical, should block power on if anything wrong with it(failed to get/ >> prepare/ enable) >> 2/ optional, could ignore it if anything wrong >> 3/ only required in some special cases, for example register r/w, and >> doesn't need to stay enabled while power on >> >> so maybe we can: >> 1/ let the device(dts) or driver decide which clock is PM clk, and add it >> using *pm_clk_add* APIs (even of_pm_clk_add_clks() if all clocks are pm clk) We have already tried adding DT binding for this. Those got correctly nacked, as this seems like a SW config and not HW config, at least in my opinion. >> >> 2/ add support for critical PM clk, which would return error to the driver >> if anything wrong >> >> 3/ make sure PM clk always be controlled(otherwise it might be unexpected >> disabled by other clocks under the same clk parent?): >> a) make sure Runtime PM is always enabled. and as discussed, we can select >> PM in ARCH_ROCKCHIP I am fine enabling PM for ARCH_ROCKCHIP, if needed. However, what I don't agree with in general, is to make a generic driver to rely on having CONFIG_PM to be set to be functional. That's to me, bad practice. I understand, this approach exists in drivers today. I assume it works, because those drivers are being used on SoCs which always has CONFIG_PM set. > > On Renesas SoCs, we only add the device's module clock with pm_clk_add(). > Drivers that don't care about properties of the module clock just call > pm_runtime_*(). That way the same driver works on different SoCs using > the same device, with and without power and/or clock domains. I understand your point and I accept your view. However, I think this is more a mindset of which way one want implement things. This has been discussed several times in the mailing list as well. Surely we can cope with SoC specific constraints in drivers as well, we already do that. In principle I think this boils done to comparing a centralized method, where the PM domain deals with clocks vs a decentralized method, where the driver deals with clocks. Both works, both have positive and negative consequences. In my experience for ARM SoCs, I have found that centralized method doesn't work well, when one need flexibility. For example, if there are strict constraints on the order of how to put device's PM resources (clocks, pinctrl, etc) in low power states. For example, to avoid clock glitches. Another problem with the PM clk is, more exactly with pm_clk_suspend|resume(), that those invokes only clk_enable|disable(). pm_clk_suspend|resume() can't call clk_prepare|unprepare(), because we don't know if we running in atomic context when those are executed. Potentially this means leaving the clocks ungated - all the time. I have though about how to fix the above, several times, but I always ends up with thinking that's it more easy, to let the driver deal with the clocks, as then the problem goes away. > > Drivers that care about properties of the module clock (mainly frequency) > can still use the clk_*() API for that. Other (optional) clocks must be > handled by the device driver itself. A comment on that; Before we the PM clk was introduced, we didn't have the clk_bulk_*() interface. To me, using clk_bulk_*() in drivers could help to simplify the code in regards to manage clocks (including SoC specific clocks) during runtime PM. Perhaps this could be an option to using PM clk, as it provides both flexibility and could manage SoC specific clocks. Kind regards Uffe