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[209.132.180.67]) by mx.google.com with ESMTP id u15-v6si2929401plk.516.2018.03.01.02.45.22; Thu, 01 Mar 2018 02:45:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j0e1LCJS; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S967203AbeCAKoX (ORCPT + 99 others); Thu, 1 Mar 2018 05:44:23 -0500 Received: from mail-io0-f181.google.com ([209.85.223.181]:38107 "EHLO mail-io0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966574AbeCAKoU (ORCPT ); Thu, 1 Mar 2018 05:44:20 -0500 Received: by mail-io0-f181.google.com with SMTP id g21so6634435ioj.5 for ; Thu, 01 Mar 2018 02:44:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=H4GY3wV9qdQCzgw5NE6i0JM69WORrm+nsNQ5VnwC6ig=; b=j0e1LCJSLjOe1YWkGIwB3luN8TVg+OQ5+1fmqesXWiVnzw7s7jrPfMqvaO3VfS1yV8 O2+pvHRHOAGkkziHvNFkHVVgQe8ChBZvJVB5kuXEZcD/hvKqvjNrEN1t8jH+G3ys4Eyf 5ZW8dUblW6DDF6Iu3zJFTVYhz/zvFA/rXWIis= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=H4GY3wV9qdQCzgw5NE6i0JM69WORrm+nsNQ5VnwC6ig=; b=h/LuZKxhk9pAoAbPnRspmT5kb+/uzP13agerIjVheMSAJokQAlhmdrKLHmVkbavf0m 2ef1G5IPwED94kCLo1k8U8R6xjIMBEskPU5r3kKGcDNoJSF/gZCAp8JlAgmC+XskiBEb EiKFGHbV6lnBJ9/Cs4LGKeS6whoV/ijMq0LWBRcD2lRdbmhgplTwNA+a8PYS2ejWygij OakM5SPJJ9ylv2EbVzJkCVmdNJ3ZgDkcjQSA7kkMm9zgVuqVJ3k/bu+xuo55GfRRAAki VA4TnbYsTVU/8OzBsUpFC+22da9rSXWuEsDx4qZIZRtIWeqs6ER3ZyMDx3oKvrtmH9mZ XCpA== X-Gm-Message-State: AElRT7FrloE6NdZbC85fPknrjZsGTuW7OExWd3FoSfVw1wAzkh5m3dwI a41JHP9yKEcF1x/Yoo3hXB9cIdb7FKkmXWPaDDOGjQ== X-Received: by 10.107.104.1 with SMTP id d1mr1364882ioc.119.1519901059164; Thu, 01 Mar 2018 02:44:19 -0800 (PST) MIME-Version: 1.0 Received: by 10.2.91.10 with HTTP; Thu, 1 Mar 2018 02:44:18 -0800 (PST) In-Reply-To: <8f328063-610f-a2e8-5f29-d3f0019384f2@st.com> References: <1519832844-28068-1-git-send-email-ludovic.Barre@st.com> <8f328063-610f-a2e8-5f29-d3f0019384f2@st.com> From: Ulf Hansson Date: Thu, 1 Mar 2018 11:44:18 +0100 Message-ID: Subject: Re: [PATCH V2 0/5] mmc: add stm32 sdmmc controller To: Ludovic BARRE Cc: Rob Herring , Maxime Coquelin , Alexandre Torgue , Gerald Baeza , Linux ARM , Linux Kernel Mailing List , devicetree@vger.kernel.org, "linux-mmc@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1 March 2018 at 10:57, Ludovic BARRE wrote: > Hi Ulf > > On 03/01/2018 10:06 AM, Ulf Hansson wrote: >> >> Hi Ludovic, >> >> On 28 February 2018 at 16:47, Ludovic Barre wrote: >>> >>> From: Ludovic Barre >>> >>> This patch serie adds support of stm32 SDMMC controller. >>> stm32h7 is the first SoC to use stm32 SDMMC controller >>> (previous SoC had pl180 controller). >> >> >> I am a not convinced this isn't a new improved variant of the pl180. >> According to register layout and the code you submitted in patch2, >> there are great similarities to pl180 and the mmci driver. > > > In fact, ST designers which created stm32-sdmmc hardware block from scratch > are the same which have done the modifications on pl180 variant (stm32 > legacy f4, f7). > So some registers or bits name seem identical (or strongly inspirited) but > the engine and features are different. Well, in that case, I assume the driver would also need work differently, but when looking at the code in patch2 this doesn't seem to be the case. > > You could find the datasheet of STM32H7x3 on: > http://www.st.com/content/ccc/resource/technical/document/reference_manual/group0/c9/a3/76/fa/55/46/45/fa/DM00314099/files/DM00314099.pdf/jcr:content/translations/en.DM00314099.pdf > > Chapters: 55 Secure digital input/output MultiMediaCard interface > (SDMMC) Thanks for sharing this. However this confirms my view, it looks exactly as a new improved mmci variant. :-) > > This hardware block has own roadmap and some features are already in the > pipe for next SoC. That's fine. I don't have a problem extending the mmci driver, even several times, as to cope with new revisions. > > For code design: like I also worked on pl180 in the past :-) > my code is inspirited of this driver. Right, that may explain things a bit. However, besides a re-name of the registers, I really think that the code execution, dealing with IRQs etc, is very similar to the mmci driver. Isn't it? So, I think it's at least worth to give it a go with the mmci driver first, to see if we can get it to work. I guess you understand why I am pushing!? This is about maintenance - and I really want to avoid having a yet another driver to maintain, unless we can extend an existing one. [...] Kind regards Uffe