Received: by 10.223.185.116 with SMTP id b49csp7354456wrg; Thu, 1 Mar 2018 04:17:59 -0800 (PST) X-Google-Smtp-Source: AG47ELuBTdWFGu6Kr1ch7hExwiHTU3uUEhxWS8MkgOuroByJEDzi0BjdIfeFUm/zql5/hZsgzp7R X-Received: by 2002:a17:902:c24:: with SMTP id 33-v6mr1789142pls.24.1519906679681; Thu, 01 Mar 2018 04:17:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519906679; cv=none; d=google.com; s=arc-20160816; b=Z9R5u+bnXMKJlwvMZHkKH7aLkt/eJIQWvXmbMcnTFi8SnkMWmVJvhePQoR0aNBOaEV wyYvUTjrKGjKoRXWuWf8C4htHb8xP6VLYsOD+QXnA47DsIySRgBBv2nXbuxgdXYbqdvn BMlIshAqi+FIA6TO+hnY4s7j1EPhBnCDnJuywSvxIKziBObrdDSkBxSVyG0EKEibO/Z9 eIDJdg3m4QzecMtL++G3+bBoRDAsfFgA+tDlpFO4re/WlUgqXl6TbJx5iJ6DOOUAr4MV /zNGHdbdxtu3qVAizFZPrlXg+xPO4y8iphNUIpfDvcb9t0CpKlMj9qpaFYMi9fQpdge+ W8Ig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:user-agent:references :message-id:in-reply-to:subject:cc:to:from:date :arc-authentication-results; bh=mmYaXPSDZAP20DIEfq4CSZRcGvwEAvrDvOa/qrTvNQw=; b=NtJGJ0kOJauc05V4pTVibbQGmzkjXyyG489vPiq0cL5XTd89aFJhwWwilPam8VcvpH 3KfczZbK3poGyq7gJ/TKC0sBOylBcAl1JRtNofxg8LhSRpsBFi01vaCSg2m1Az3LSqE5 cWD9yc0MfqQupdXo8OMW2G0dXCG/DcuUwRxPobPfW8xVl6Ab8v/hoy65vmT/rh9HxNo/ qRhN46AjtwxyxwWcOg5OfRLRjH7v7kYstJJVo7j1U2hbN4jJaNJPfH4kVcuHu0xU+cd+ saAUDscu40RD+VrLDuyy1VpRQrGp2RJ6RdOGk/idzvQvegg8egoxamY5sra5nv5ouqPR YcMA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b89-v6si2986452plb.809.2018.03.01.04.17.43; Thu, 01 Mar 2018 04:17:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030354AbeCAMQz (ORCPT + 99 others); Thu, 1 Mar 2018 07:16:55 -0500 Received: from Galois.linutronix.de ([146.0.238.70]:50896 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030253AbeCAMQy (ORCPT ); Thu, 1 Mar 2018 07:16:54 -0500 Received: from hsi-kbw-5-158-153-52.hsi19.kabel-badenwuerttemberg.de ([5.158.153.52] helo=nanos.tec.linutronix.de) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1erN5B-0005My-9U; Thu, 01 Mar 2018 13:13:09 +0100 Date: Thu, 1 Mar 2018 13:16:47 +0100 (CET) From: Thomas Gleixner To: Rasmus Villemoes cc: Rob Herring , Shawn Guo , Jason Cooper , Marc Zyngier , Andy Tang , Alexander Stein , linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 1/2] irqchip: add support for Layerscape external interrupt lines In-Reply-To: <20180223210901.23480-2-rasmus.villemoes@prevas.dk> Message-ID: References: <20180125150230.7234-1-rasmus.villemoes@prevas.dk> <20180223210901.23480-1-rasmus.villemoes@prevas.dk> <20180223210901.23480-2-rasmus.villemoes@prevas.dk> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 23 Feb 2018, Rasmus Villemoes wrote: > +#include > +#include > +#include > +#include of.h is already included from of_irq.h and of_address.h > +#include > +#include > +static int > +ls_extirq_set_type(struct irq_data *data, unsigned int type) > +{ > + irq_hw_number_t hwirq = data->hwirq; > + struct extirq_chip_data *chip_data = data->chip_data; > + u32 value, mask; Please order local variables in reverse fir tree fashion whenever possible. That's way simpler to read: struct extirq_chip_data *chip_data = data->chip_data; irq_hw_number_t hwirq = data->hwirq; u32 value, mask; > + > + if (chip_data->bit_reverse) > + mask = 1U << (31 - hwirq); > + else > + mask = 1U << hwirq; > + > + switch (type) { > + case IRQ_TYPE_LEVEL_LOW: > + type = IRQ_TYPE_LEVEL_HIGH; > + value = mask; > + break; > + case IRQ_TYPE_EDGE_FALLING: > + type = IRQ_TYPE_EDGE_RISING; > + value = mask; > + break; > + case IRQ_TYPE_LEVEL_HIGH: > + case IRQ_TYPE_EDGE_RISING: > + value = 0; > + break; > + default: > + return -EINVAL; > + } > + > + regmap_update_bits(chip_data->syscon, chip_data->intpcr, mask, value); > + > + data = data->parent_data; > + return data->chip->irq_set_type(data, type); irq_chip_set_type_parent() Thanks, tglx