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[209.132.180.67]) by mx.google.com with ESMTP id s23-v6si2528548plr.109.2018.03.01.05.59.13; Thu, 01 Mar 2018 05:59:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cJolsdgN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031026AbeCAN6b (ORCPT + 99 others); Thu, 1 Mar 2018 08:58:31 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:55517 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1031001AbeCAN6Z (ORCPT ); Thu, 1 Mar 2018 08:58:25 -0500 Received: by mail-wm0-f67.google.com with SMTP id q83so11928324wme.5 for ; Thu, 01 Mar 2018 05:58:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nVrukGrRijRZWu+qMWPxMCwlS23q444xkQmkLHiDLo8=; b=cJolsdgNVtXMUCa3SjU9ychsLEUf8MVOW4m4rOxLjvWzb4n/FNzsumb9vTmU5iXBcP tGTth4VID4oivU+KhP+tb0o8P+4nIQ5aFFvQN6Y01gof0vAF09AYRB8ZuIAFfn5+2cUG s49h0RBLSJBJTAMHwsHxRpXGetpjvGoHYZto0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nVrukGrRijRZWu+qMWPxMCwlS23q444xkQmkLHiDLo8=; b=hUlTTLX7RRhRKg0LOsEn5E3QxAVz7Fw5ZX7M2X4ZujCM5xAQUScPofsYsyrw1Rsy3C zKZJh4sTkEirdetH82MLsbCVzzD+non3BlifJmk8vI14pTnSgIm+uD0wr47z1VgkIpE3 ZXbxGahVp3UXFUB96vo2poDcdbIx91j1KMYwa4hwFo0WXFqGSfrpQyZeVmShO7OyiBjG L4RnwJnLUDZR3pCb9FN72217Eo4zQ5OFVnbM178aWPCrd2TCLu13CEmwJ//8DUJrvGls aYQJ1axz9I+s/dtzMVG9ZTKG5+HAcpvlK42a4A073ce+qvxSuwni+tC1UpmEBrgkFYOD Q8NA== X-Gm-Message-State: APf1xPBjjCsB0poFh8/D9yueAB473/zQJ5JeIh/neCNwDfHDB8kTOcWt HMvEd9SDSyW9+NqiGsCNjX47Jg== X-Received: by 10.28.124.5 with SMTP id x5mr1745968wmc.11.1519912704120; Thu, 01 Mar 2018 05:58:24 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.14.109]) by smtp.gmail.com with ESMTPSA id e6sm3826304wra.67.2018.03.01.05.58.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 01 Mar 2018 05:58:23 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, robin.murphy@arm.com, arnd@arndb.de, loic.pallardy@st.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v2 1/2] dt-bindings: stm32: Add bindings for Extended TrustZone Protection Date: Thu, 1 Mar 2018 14:58:05 +0100 Message-Id: <20180301135806.19982-2-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20180301135806.19982-1-benjamin.gaignard@st.com> References: <20180301135806.19982-1-benjamin.gaignard@st.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Extended TrustZone Protection driver is very basic and only needs to know where are the registers (no clock, no interrupt) Signed-off-by: Benjamin Gaignard --- .../bindings/arm/stm32/st,stm32mp1-etzpc.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/stm32/st,stm32mp1-etzpc.txt diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32mp1-etzpc.txt b/Documentation/devicetree/bindings/arm/stm32/st,stm32mp1-etzpc.txt new file mode 100644 index 000000000000..9407e37f7d15 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32mp1-etzpc.txt @@ -0,0 +1,25 @@ +STMicroelectronics STM32 Extended TrustZone Protection driver + +Required properties: + - compatible : value should be "st,stm32mp1-etzpc" + - reg : physical base address of the IP registers and length of memory + mapped region. + - protected-devices: list of phandle of devices protected by etzpc. + Because etzpc driver rely on the phandle index in + the list, holes must be filled with a disabled node. + +Example for stm32mp1: + +reserved: disabled_node { + status = "disabled"; +}; + +etzpc: etzpc@5c007000 { + compatible = "st,stm32mp1-etzpc"; + reg = <0x5c007000 0x400>; + protected-devices = <&usart1>, + <&spi6>, + <&i2c4>, + <&reserved>, + <&rng1>; +}; -- 2.15.0