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[209.132.180.67]) by mx.google.com with ESMTP id f1-v6si3413127pld.744.2018.03.01.11.22.42; Thu, 01 Mar 2018 11:22:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@intel-com.20150623.gappssmtp.com header.s=20150623 header.b=YJXpWYyI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161298AbeCATVS (ORCPT + 99 others); Thu, 1 Mar 2018 14:21:18 -0500 Received: from mail-oi0-f47.google.com ([209.85.218.47]:41489 "EHLO mail-oi0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1161188AbeCATVO (ORCPT ); Thu, 1 Mar 2018 14:21:14 -0500 Received: by mail-oi0-f47.google.com with SMTP id g5so5325407oiy.8 for ; Thu, 01 Mar 2018 11:21:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel-com.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=eAgLBlsStzs31yOatT4ocHh14AQGuobyZU884lR58A4=; b=YJXpWYyIEKlS3cJMR1+HTudqv3OZYxrSZwTpZRmeqjxpJKDvuVU5jba+u+gm92lb70 B/Lo1z3GQ/pcqvpWk/gNUDStaRVPwJKT86Gvsk6x3Rp7lqyPyG6096DTwAumPZoVLPcw wDauK7Ti4kfO5SqJJCkd1SVjYHbfb/KtEMpH18hFTcjxZ3a2F4rHCocI0VimnSUTQnYv 2/AykecV7cCCImLWzUU7vyoDJ2nDXrszn4sUyfvyFFdoALB88IEzsUVEhwC5PgRBEgX1 paebtOc7/qLZruDre55rk0jQqt913WxkJ6FSrOvN/S1X3iJ4dRsZ0KvH03KqYXKTVky/ Lx/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=eAgLBlsStzs31yOatT4ocHh14AQGuobyZU884lR58A4=; b=ZmJMTFqtRbik2zkTz9HshldS1EKsLjINzabFiKBdNiEj3Ft4YMZwXinM608ZwcNE5e 8ublCiK4wb0WuZYN9aAW7hpSuz83TK9PhhIsAFLJYMV3PEQU1O8HLPp+hy80EM6tHjEx K3xBYQKN/dSHmL/2sPMZsyrDcA4sPNBcunW5eTuU0gQ0OACgiv9OwL12WINLtOMoApyF lM2YaGfIE0UEOtW+2IKIGTHTfMqZBRZnAsjXzxTOnq9fD4/7s4GrWiEYI3wPQE3XHNWs 5YzJcSz3H+BrBmLpX3f47lpOxm6jiiXjsGnkdgL9RitmJGPfzPrXbeRI2E2aCCodELL5 CBdw== X-Gm-Message-State: AElRT7Ftme5y/H65/v0Z3x/x72v30GUHkFHtn9k27k1b5hlJQ4KUGL6I wOAgpnT4DY0vlLzbEFQJmlRncr+H8wy9fmG07q96gw== X-Received: by 10.202.27.1 with SMTP id b1mr2067283oib.110.1519932073426; Thu, 01 Mar 2018 11:21:13 -0800 (PST) MIME-Version: 1.0 Received: by 10.157.81.210 with HTTP; Thu, 1 Mar 2018 11:21:13 -0800 (PST) In-Reply-To: <1519876569.4592.4.camel@au1.ibm.com> References: <20180228234006.21093-1-logang@deltatee.com> <1519876489.4592.3.camel@kernel.crashing.org> <1519876569.4592.4.camel@au1.ibm.com> From: Dan Williams Date: Thu, 1 Mar 2018 11:21:13 -0800 Message-ID: Subject: Re: [PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory To: benh@au1.ibm.com Cc: Logan Gunthorpe , Linux Kernel Mailing List , linux-pci@vger.kernel.org, linux-nvme@lists.infradead.org, linux-rdma , linux-nvdimm , linux-block@vger.kernel.org, Stephen Bates , Christoph Hellwig , Jens Axboe , Keith Busch , Sagi Grimberg , Bjorn Helgaas , Jason Gunthorpe , Max Gurtovoy , =?UTF-8?B?SsOpcsO0bWUgR2xpc3Nl?= , Alex Williamson , Oliver OHalloran Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Feb 28, 2018 at 7:56 PM, Benjamin Herrenschmidt wrote: > On Thu, 2018-03-01 at 14:54 +1100, Benjamin Herrenschmidt wrote: >> On Wed, 2018-02-28 at 16:39 -0700, Logan Gunthorpe wrote: >> > Hi Everyone, >> >> >> So Oliver (CC) was having issues getting any of that to work for us. >> >> The problem is that acccording to him (I didn't double check the latest >> patches) you effectively hotplug the PCIe memory into the system when >> creating struct pages. >> >> This cannot possibly work for us. First we cannot map PCIe memory as >> cachable. (Note that doing so is a bad idea if you are behind a PLX >> switch anyway since you'd ahve to manage cache coherency in SW). > > Note: I think the above means it won't work behind a switch on x86 > either, will it ? The devm_memremap_pages() infrastructure allows placing the memmap in "System-RAM" even if the hotplugged range is in PCI space. So, even if it is an issue on some configurations, it's just a simple adjustment to where the memmap is placed.