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[209.132.180.67]) by mx.google.com with ESMTP id f1-v6si3413127pld.744.2018.03.01.11.24.14; Thu, 01 Mar 2018 11:24:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=dt3m7pl7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161259AbeCATXH (ORCPT + 99 others); Thu, 1 Mar 2018 14:23:07 -0500 Received: from mail-ua0-f194.google.com ([209.85.217.194]:38273 "EHLO mail-ua0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1161195AbeCATXF (ORCPT ); Thu, 1 Mar 2018 14:23:05 -0500 Received: by mail-ua0-f194.google.com with SMTP id f5so4615293uam.5 for ; Thu, 01 Mar 2018 11:23:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=YplxC9X3Rzd/Q1FWvQVYIYsgQlspyiMvec/eHUeKlN0=; b=dt3m7pl7ZR8eONBBKb8z5E6phJ/iq1+cg0KJLk8sPQAu5z/3xFA3B5B06p/A00xKNj lLGGJ5t7O247/9lTLJhLgArqbxkQUrUhwleoY6zNmUYcdGT4qkYM7QEWxEpqtBgPYPv3 yo/L5EjPbHRSm19ejzZ/dMjoOgT7LMAZYeyzM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=YplxC9X3Rzd/Q1FWvQVYIYsgQlspyiMvec/eHUeKlN0=; b=MaYuUB21zuUl40++vqscXhVPW6sfRb3mP0iBHM2oIeBvzKnQ6uTJTQqZY6PMk2yOqS nnMcTF2jPQSnJtFhZ7UYWkOO4jTx+C8Vb3oa4PmljXQDzTBPisGp+iWBnIlePT8c5/BR h58wLOabrqzXMUz/zI8Me4JLfgPER9E0DqM/jb6AYgsgslxH+wHKSz3kJgDEGqpUdtYj hM/IUfVgVjXeMY3gP3ddLnpLBtvkRiXWqZsKttSbJbLFw7lKtdMjOTtWbm8LdS03dTzY NZbJleH6AD0jxx3fRi8Rz1UMFNqnwpEbHhba/alCkzTYVHw36EF5X0XS8vg1Om0mykAi Q+Qg== X-Gm-Message-State: APf1xPA0AIc/FPDEy/k/tFL4biwyaQztuBbbzhvQBmMM0716wx6WUfGF iKPajFCMep7ZR/yZIhbNjK8m6i2OsouaY7bFH4itIg== X-Received: by 10.176.83.88 with SMTP id y24mr2006165uay.121.1519932184226; Thu, 01 Mar 2018 11:23:04 -0800 (PST) MIME-Version: 1.0 References: <20180301184335.248378-1-djkurtz@chromium.org> In-Reply-To: From: Daniel Kurtz Date: Thu, 01 Mar 2018 19:22:52 +0000 Message-ID: Subject: Re: [PATCH v2] earlycon: Allow specifying a uartclk in options To: Andy Shevchenko Cc: adurbin@chromium.org, Brian Norris , corbet@lwn.net, Greg Kroah-Hartman , jslaby@suse.com, mingo@kernel.org, Thomas Gleixner , cdall@linaro.org, paulmck@linux.vnet.ibm.com, marc.zyngier@arm.com, frederic@kernel.org, dwmw@amazon.co.uk, tom.saeger@oracle.com, zohar@linux.vnet.ibm.com, alexander.levin@verizon.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 1, 2018 at 11:47 AM Andy Shevchenko wrote: > On Thu, Mar 1, 2018 at 8:43 PM, Daniel Kurtz wrote: > Please, hold on with new versions. > I'm not satisfied (yet?) by the approach. Copying over your comment on v1: > It needs to be discussed. Sure. > First of all, if you are going to do this you need to add a parse of > human readable formats (IIRC kernel has helpers), i.e. "48M", "38.4M" > and so on. > Next, I was under impression that purpose of earlycon (in difference > to earlyprintk) is to re-use existing drivers as fully as possible. > So, what exactly happens in your case? Are your driver lacks of > properly set clock? Or earlycon does simple not utilizing this > information? "earlycon simply does not utilize the information". earlycon parses iotype, mapbase and baud (from options). However, it is hard-coded to assume that the clock used to generate the UART bitclock is always "BASE_BAUD * 16" (1843200). While this may be true for many UARTs, it isn't true for AMD's CZ/ST which has a 8250_dw and uses a fixed 48 MHz clock. The main 8250_dw driver uses devm_clk_get to get the "baudclk" and uses its rate to initialize uartclk. For AMD CZ/ST, this "baudclk" is actually a set up in acpi_apd.c when there is an acpi match for "AMD0020", with a rate read from the .fixed_clk_rate param of the corresponding apd_device_desc. This patch attempts to add a way to inform earlycon about this clock. As noted above, the information is actually already in the kernel and used by 8250_dw - I would happy be to hear recommendations for wiring this data into earlycon that doesn't require adding another command line arg. I see that support was also added recently to earlycon to let it use ACPI SPCR to choose a console and configure its parameters... but AFAICT, this path also doesn't allow specifying the uart clock. -Dan