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[209.132.180.67]) by mx.google.com with ESMTP id g1-v6si3462793pld.322.2018.03.01.12.03.39; Thu, 01 Mar 2018 12:03:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=MSYaADQP; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161457AbeCAUC2 (ORCPT + 99 others); Thu, 1 Mar 2018 15:02:28 -0500 Received: from mail-qt0-f170.google.com ([209.85.216.170]:44321 "EHLO mail-qt0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1161432AbeCAUC0 (ORCPT ); Thu, 1 Mar 2018 15:02:26 -0500 Received: by mail-qt0-f170.google.com with SMTP id g60so9146226qtd.11; Thu, 01 Mar 2018 12:02:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=WDyIH1krvqTZxOKUIpkFGl78BGSAW3guXkG36iui3MQ=; b=MSYaADQPFM0ayMan5zwsLlAMkp5jGmXcnYrneZOBWNU/aa1+8HMjRVWkIxEfE1MBdW 8tMWDNAdD1YLJpsJ9Eea0nIWwgG8siHczEaYAP8pxiwhFgc2/JDWTLc+jfkv93XaAaxd K00ZlbRdBI0wBiVftB921QhugUvBeA3ekI/xgf+ez01LqlUPmrMaN8XjdfvjZpxD0GlR TQdZlqiD/+sAYFMwqqpHlCvrhUKnMiFqbHAxWeUTNU/IWEdcurbShurpK4D4YAEBzX6e EPHC9jdXpfxB+jkuveLnOn4NPGle28zhJcPPe3AcS+GoPJX0FzMdVgayMb8zUXYML6QW oXdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=WDyIH1krvqTZxOKUIpkFGl78BGSAW3guXkG36iui3MQ=; b=BcuYUgy8bb9818kM65J4NZ3o/dydXVaQpbFRJjl0y0qpZSQEgFPHIhAfPPrm5SpHmq vXrr+TpzPsdGuUTtxUba5k8JA7e9WBES3NZorovsgiyhgLg/NmNjci7Zo9YEPw3OesWf ekCBYzeHuPYEpra2qYGhr3lQJn0qTnxvLq9MiprugmUlMu6J7HGstmogbb4A7htEOYUC zWIqmWOFq/NBV7jnG/iAw9JhY5bw/A6dbBtzFKNbzdvx6myP95Ats3870iGjF93oAGB6 Ry2EeOO8qSAHQ9bcon0+JLzCJ50rNGGFHiQJf44cRBrW1Bxra9muJSplfVfBLFpAudcM D8Nw== X-Gm-Message-State: AElRT7HDBjxnkrdl5pO0rlR4179mAASHoPUk1CtuRjO8Ne5f4b2GhcYs 1pGYvfp8LC27QsHyaRcBXw//FXqdbpOi8THbx48= X-Received: by 10.200.26.79 with SMTP id q15mr4650817qtk.174.1519934545169; Thu, 01 Mar 2018 12:02:25 -0800 (PST) MIME-Version: 1.0 Received: by 10.12.195.80 with HTTP; Thu, 1 Mar 2018 12:02:24 -0800 (PST) In-Reply-To: References: <20180301184335.248378-1-djkurtz@chromium.org> From: Andy Shevchenko Date: Thu, 1 Mar 2018 22:02:24 +0200 Message-ID: Subject: Re: [PATCH v2] earlycon: Allow specifying a uartclk in options To: Daniel Kurtz Cc: adurbin@chromium.org, Brian Norris , Jonathan Corbet , Greg Kroah-Hartman , Jiri Slaby , Ingo Molnar , Thomas Gleixner , Christoffer Dall , "Paul E. McKenney" , Marc Zyngier , Frederic Weisbecker , David Woodhouse , Tom Saeger , Mimi Zohar , "Levin, Alexander (Sasha Levin)" , Linux Documentation List , Linux Kernel Mailing List , "open list:SERIAL DRIVERS" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 1, 2018 at 9:22 PM, Daniel Kurtz wrote: > On Thu, Mar 1, 2018 at 11:47 AM Andy Shevchenko > wrote: > "earlycon simply does not utilize the information". > > earlycon parses iotype, mapbase and baud (from options). However, it is > hard-coded to assume that the clock used to generate the UART bitclock is > always "BASE_BAUD * 16" (1843200). While this may be true for many UARTs, > it isn't true for AMD's CZ/ST which has a 8250_dw and uses a fixed 48 MHz > clock. The main 8250_dw driver uses devm_clk_get to get the "baudclk" and > uses its rate to initialize uartclk. For AMD CZ/ST, this "baudclk" is > actually a set up in acpi_apd.c when there is an acpi match for "AMD0020", > with a rate read from the .fixed_clk_rate param of the corresponding > apd_device_desc. > > This patch attempts to add a way to inform earlycon about this clock. As > noted above, the information is actually already in the kernel and used by > 8250_dw - I would happy be to hear recommendations for wiring this data > into earlycon that doesn't require adding another command line arg. And it should not require that for sure! I would look to this later. It's late here. I need to do a bit of research for the answer. > I see that support was also added recently to earlycon to let it use ACPI > SPCR to choose a console and configure its parameters... but AFAICT, this > path also doesn't allow specifying the uart clock. Fix your firmware then. It should set console to 115200 like (almost) everyone does. Okay, configures a necessary IPs to feed UART with expected 1.8432M clock. -- With Best Regards, Andy Shevchenko