Received: by 10.223.185.116 with SMTP id b49csp8266489wrg; Thu, 1 Mar 2018 21:32:18 -0800 (PST) X-Google-Smtp-Source: AG47ELvy8baMx4GtvD0AGKH3wqYIWen8Vaxo6GKESiKXGD+bYCqhgDvzU1fVqMN8pWwFSpgDi7DT X-Received: by 10.98.36.25 with SMTP id r25mr4568781pfj.106.1519968738765; Thu, 01 Mar 2018 21:32:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519968738; cv=none; d=google.com; s=arc-20160816; b=EnoJ490fdmsX1obNM38Y6hpgH5qJyeUw0kkNJl5wtM0FrpeKnw/jvszk9ZfdnMqG3t k5P2hqEW4yJNwSo3Dm7gGqHIazv7f2keA/jwQ7XZGkruIeE6AJDGa9jpcyzVd8sqCstb ah1re1iOCaVRuuWrPWO6NiglWOZDdhufEmzgr9OCc9dArhQnpMAYccWLzYutZxucFMEN GoilXs3B+OPjt99mhZJnjYhDHPuSoztEVqIMPtLP2kGaOHJFz5NdbupqbSQKinp9PQRv HXsKN9UjL2wixo5SDOZC76ZKtceHuG99Ab/m39zMiHna+q8PgRLLYr/0Bz9Fk1t7Qg4Z iCPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=NcNrS/AurWtYs8GOe4tVJxPyFNKpfhEu/qhnjS+RemY=; b=H+FKpXoPrS1R54Tsm6xQYo9CQjkrmWxTtZUmny1ixkB37xiZmYLM8/xFeEbxfmfn7u Np2ZwnaeXOoYmjcwPalHi/78hnCXp33/Wu1KnIOFGCXYJ9R9bNCrH+hyHYPLEP4RV6JL AWdLrw9gMYXzbeCHdU5pKlCu/rtOWzV+9gbzNNgk2/Q0ZQurOc+YU5QY7jm3QzXDpr6h amKqFo/RREtbRw/DUMSGwKIxsCk1NpIEVmrBk5sm8PxYLZktGtKOwKkX3yK/d7OogAec ysKY8Xec7MjwHSR2DzoPT2RcPgjBlLBJzLASGxheWfjNuRT0FQtfMLmr2JYX94GjKryz JJrw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x1-v6si4201184pln.571.2018.03.01.21.32.01; Thu, 01 Mar 2018 21:32:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1164644AbeCBENX (ORCPT + 99 others); Thu, 1 Mar 2018 23:13:23 -0500 Received: from zxshcas1.zhaoxin.com ([180.169.121.91]:48863 "EHLO ZXSHCAS1.zhaoxin.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1164198AbeCBENW (ORCPT ); Thu, 1 Mar 2018 23:13:22 -0500 Received: from zxbjmbx3.zhaoxin.com (10.29.252.165) by ZXSHCAS1.zhaoxin.com (10.28.252.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Fri, 2 Mar 2018 12:13:18 +0800 Received: from timguo-System-Product-Name.zhaoxin.com (10.29.8.93) by zxbjmbx3.zhaoxin.com (10.29.252.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Fri, 2 Mar 2018 12:13:17 +0800 From: David Wang To: , , , , , , , , CC: , , , , , , , , David Wang Subject: [PATCH] Delete some unusefull operations for centaur CPU/platform Date: Fri, 2 Mar 2018 12:11:48 +0800 Message-ID: <1519963908-4359-1-git-send-email-davidwang@zhaoxin.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.29.8.93] X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To zxbjmbx3.zhaoxin.com (10.29.252.165) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For Centaur CPU, the ucode will make sure that each CPU core can keep cache coherency with each other when the CPU core entering to any C state. So the cache flush operations when enter C3 is not necessary and will cause large C3 enter/exit latency. And the bus master disable operation when CPU core entering C3 state is not needed too. Because the chipset will automatically do this operation. Signed-off-by: David Wang --- arch/x86/kernel/acpi/cstate.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c index dde437f..1cd357b 100644 --- a/arch/x86/kernel/acpi/cstate.c +++ b/arch/x86/kernel/acpi/cstate.c @@ -51,6 +51,18 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, if (c->x86_vendor == X86_VENDOR_INTEL && (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f))) flags->bm_control = 0; + + if (c->x86_vendor == X86_VENDOR_CENTAUR) { + /* + * on all centaur CPUs, sw need not execute cache flush operation + * when entering C3 type State. + * + * On all Centaur platforms, sw need not execute ARB_DISABLE while + * entering C3 type state. + */ + flags->bm_check = 1; + flags->bm_control = 0; + } } EXPORT_SYMBOL(acpi_processor_power_init_bm_check); -- 1.9.1