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[209.132.180.67]) by mx.google.com with ESMTP id z3si3614759pgs.71.2018.03.01.23.07.58; Thu, 01 Mar 2018 23:08:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=w3CuiXCq; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1164151AbeCBG0T (ORCPT + 99 others); Fri, 2 Mar 2018 01:26:19 -0500 Received: from fllnx210.ext.ti.com ([198.47.19.17]:43500 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933010AbeCBG0R (ORCPT ); Fri, 2 Mar 2018 01:26:17 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id w226Q1uY032570; Fri, 2 Mar 2018 00:26:01 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1519971961; bh=jaQ8ZsySetMNos5EB8tOBzz1TBvd5RQfXkjJ1xmijBA=; h=Subject:To:References:CC:From:Date:In-Reply-To; b=w3CuiXCqOJAniqxOsZE0DwsZYV9EJOFMyjs71+qWJap/GHY2mlkqzuv0bjxi5qo3j hNBNYu9YlS0ZjL+DxY+Ru7vtGWGVr7iVnmk1RYFR2sBl8tif0GzLHxZKeii3LY/Wt8 SmDbYU1JY2S3Duzh8Yn06FirmPVBOBmpZFLnL4M0= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w226Q17D007428; Fri, 2 Mar 2018 00:26:01 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Fri, 2 Mar 2018 00:26:01 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Fri, 2 Mar 2018 00:26:01 -0600 Received: from [172.24.190.233] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w226PwIb032295; Fri, 2 Mar 2018 00:25:58 -0600 Subject: Re: [PATCH v3 1/2] dt-bindings: add bindings doc for HiSilicon INNO USB2 PHY To: Shawn Guo References: <1519888940-23235-1-git-send-email-shawn.guo@linaro.org> <1519888940-23235-2-git-send-email-shawn.guo@linaro.org> CC: Rob Herring , Jianguo Sun , Jiancheng Xue , , , Pengcheng Li From: Kishon Vijay Abraham I Message-ID: Date: Fri, 2 Mar 2018 11:55:57 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.7.0 MIME-Version: 1.0 In-Reply-To: <1519888940-23235-2-git-send-email-shawn.guo@linaro.org> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thursday 01 March 2018 12:52 PM, Shawn Guo wrote: > From: Pengcheng Li > > It adds device tree bindings document for HiSilicon INNO USB2 PHY. > > Signed-off-by: Pengcheng Li > Signed-off-by: Jiancheng Xue > Signed-off-by: Shawn Guo > --- > .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 52 ++++++++++++++++++++++ > 1 file changed, 52 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt > > diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt > new file mode 100644 > index 000000000000..b563cf54ca7b > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt > @@ -0,0 +1,52 @@ > +HiSilicon INNO USB2 PHY > + > +Required properties: > +- compatible: Should be one of the following strings: > + "hisilicon,inno-usb2-phy", > + "hisilicon,hi3798cv200-usb2-phy". > +- reg: Should be the address space for PHY configuration register in peripheral > + controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798cv200 SoC. > +- #phy-cells: Should be 1. The specifier is the index of the PHY port to > + reference. This can be '0' if the consumers directly use phandle to the subnodes. Thanks Kishon