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[209.132.180.67]) by mx.google.com with ESMTP id j5si5080292pfe.334.2018.03.02.08.29.13; Fri, 02 Mar 2018 08:29:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1033084AbeCBPoy (ORCPT + 99 others); Fri, 2 Mar 2018 10:44:54 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:33835 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S936325AbeCBPor (ORCPT ); Fri, 2 Mar 2018 10:44:47 -0500 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w22FiO1n022136; Fri, 2 Mar 2018 16:44:28 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2gaytjhuw0-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 02 Mar 2018 16:44:28 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1254C3A; Fri, 2 Mar 2018 15:44:28 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas24.st.com [10.75.90.94]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D8DD41136; Fri, 2 Mar 2018 15:44:27 +0000 (GMT) Received: from SAFEX1HUBCAS21.st.com (10.75.90.44) by Safex1hubcas24.st.com (10.75.90.94) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 2 Mar 2018 16:44:27 +0100 Received: from localhost (10.201.23.68) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 2 Mar 2018 16:44:27 +0100 From: yannick fertre To: Vikas Manocha , Benjamin Gaignard , Yannick Fertre , Philippe Cornu , Patrice Chotard , Patrick DELAUNAY , Christophe KERELLO , Archit Taneja , Andrzej Hajda , "Laurent Pinchart" , David Airlie , Brian Norris , Bhumika Goyal , Gustavo Padovan , "Maarten Lankhorst" , Sean Paul , Albert Aribaud , "Simon Glass" , Anatolij Gustschin , Thierry Reding CC: , , Subject: [PATCH v2 08/10] arm: dts: stm32: add dsi for STM32F746 Date: Fri, 2 Mar 2018 16:44:09 +0100 Message-ID: <1520005451-23217-9-git-send-email-yannick.fertre@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1520005451-23217-1-git-send-email-yannick.fertre@st.com> References: <1520005451-23217-1-git-send-email-yannick.fertre@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.23.68] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2018-03-02_08:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add mipi dsi bridge node in device-tree. Signed-off-by: yannick fertre --- arch/arm/dts/stm32f746.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index e4d32bf..4ec954d 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -332,6 +332,18 @@ u-boot,dm-pre-reloc; status = "disabled"; }; + + dsi: dsi@40016c00 { + compatible = "st,stm32-dsi"; + reg = <0x40016C00 0x800>; + resets = <&rcc STM32F7_APB2_RESET(DSI)>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>, + <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>, + <&clk_hse>; + clock-names = "pclk", "px_clk", "ref"; + u-boot,dm-pre-reloc; + status = "disabled"; + }; }; }; -- 1.9.1