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[209.132.180.67]) by mx.google.com with ESMTP id u17si5260051pgv.116.2018.03.03.00.34.59; Sat, 03 Mar 2018 00:35:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@cogentembedded-com.20150623.gappssmtp.com header.s=20150623 header.b=lBd++Z5g; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751874AbeCCId7 (ORCPT + 99 others); Sat, 3 Mar 2018 03:33:59 -0500 Received: from mail-lf0-f65.google.com ([209.85.215.65]:32906 "EHLO mail-lf0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751608AbeCCId5 (ORCPT ); Sat, 3 Mar 2018 03:33:57 -0500 Received: by mail-lf0-f65.google.com with SMTP id o145so16491827lff.0 for ; Sat, 03 Mar 2018 00:33:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=o3/CBO8SJPWQ9B5lTHrSUTGsnd0SF1jYHa7QW6L2yaY=; b=lBd++Z5gw7q7vxz5PqPixC713PK11Yp1Izwv3lfiHJ48lunFwXrnZZvm858v0fZhzT Mq0C+ccC0DFaojiMtm1ZmahtUrKmp5UvwDZ80QDr+g7mdEa7rYQwbbgIBjksj8yc5Tsn FCy6X/22vV8jRtLVqEwSeDHN3EtaLk3UUelWjvz+hpYVfqWr6p5l6cSJMWpdu01lqH1c ZbRg3pWA2Ncv2QsX9nFAMZ3ym+41hZbHsV6yQm6f72qSOHZw2dv5e8g/v2RtLyR5QwMG ZGR5HTs4vSj5QD+NjghlPMu/n1knULd8hBeYQ1WKvZIoyimWfC1Wl35DX9UdHjkxe76g 0z3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=o3/CBO8SJPWQ9B5lTHrSUTGsnd0SF1jYHa7QW6L2yaY=; b=ZUxgNJZJiFIjOYAx4VAnXnRM7VTp3G3oF6jwvC7xR8gCJv0K07YqFChIQHbRsbSmX7 RI1g9R19XeBwRokCK6PYEAVP4WsTj7NDbmNkxfFs7dSiulUmfx4nrF9kErM+ZLo2PISM XTEiS8hLW8ljTMSrTW5ZU9TUpGzjur+sbmN9pcZuSt3MOmSBx1W9IEt77RR4C1ueO3eX lIBcKlcIeAJJk0GJTz8+cDNl8qO0Y8p63Ss8y8+caK9R6yRQwKBlCuozg5I5mKKyBr+2 DsGXUZb4Gj/4NWHR1IaCpusb5TWxZ1KtdX3GB0JO5ZmfdD40eDwfALdqsJMkUk8LK5Op pGWg== X-Gm-Message-State: APf1xPDtx2Ao0m0g/S9zcf2b6v4MYJUjO15D1NQKCmgq6b5D13FNLilB pwmLjB08H/tRWJ4pDvk0ZEjHrg== X-Received: by 10.46.118.5 with SMTP id r5mr5282187ljc.11.1520066035955; Sat, 03 Mar 2018 00:33:55 -0800 (PST) Received: from [192.168.4.126] ([31.173.82.98]) by smtp.gmail.com with ESMTPSA id h71sm1699576ljh.77.2018.03.03.00.33.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Mar 2018 00:33:55 -0800 (PST) Subject: Re: [PATCH v4 4/6] MIPS: mscc: add ocelot PCB123 device tree To: Alexandre Belloni , James Hogan , Ralf Baechle Cc: Allan Nielsen , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org References: <20180302224811.26840-1-alexandre.belloni@bootlin.com> <20180302224811.26840-5-alexandre.belloni@bootlin.com> From: Sergei Shtylyov Message-ID: <39189775-0c56-93b6-21e5-ac4d814d1879@cogentembedded.com> Date: Sat, 3 Mar 2018 11:33:55 +0300 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <20180302224811.26840-5-alexandre.belloni@bootlin.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello! On 3/3/2018 1:48 AM, Alexandre Belloni wrote: > Add a device tree for the Microsemi Ocelot PCB123 evaluation board. > > Cc: Rob Herring > Cc: devicetree@vger.kernel.org > Signed-off-by: Alexandre Belloni [...] > diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts > new file mode 100644 > index 000000000000..42bd404471f6 > --- /dev/null > +++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts > @@ -0,0 +1,27 @@ > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ > +/* Copyright (c) 2017 Microsemi Corporation */ > + > +/dts-v1/; > + > +#include "ocelot.dtsi" > + > +/ { > + compatible = "mscc,ocelot-pcb123", "mscc,ocelot"; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + memory { Needs to be "memory@0" as you have the "regs" prop. > + device_type = "memory"; > + reg = <0x0 0x0e000000>; > + }; > +}; [...] MBR, Sergei