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[95.31.14.149]) by smtp.gmail.com with ESMTPSA id h13sm1945761lfg.45.2018.03.03.12.58.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Mar 2018 12:58:01 -0800 (PST) Date: Sun, 4 Mar 2018 00:02:04 +0300 From: Alexander Sergeyev To: David Woodhouse Cc: Ingo Molnar , Thomas Gleixner , "H. Peter Anvin" , x86@kernel.org, Kyle Huey , Greg Kroah-Hartman , Peter Zijlstra , linux-kernel@vger.kernel.org Subject: spectre v2 microcodes blacklist (march update) Message-ID: <20180303210204.GA6148@localhost.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline User-Agent: mtt Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, the microcode revision guidance from Intel is revised once again [1] (1 Mar). It looks like the following: >Intel document only clears the 0xc2 microcode on *some* parts with CPUID 506E3 >(INTEL_FAM6_SKYLAKE_DESKTOP stepping 3). For the Skylake H/S platform it's OK >but for Skylake E3 which has the same CPUID it isn't (yet) cleared. is no longer a problem. CPUID 506E3 with both Skylake H/S and Skylake Xeon E3 is labelled as "production" now. Could we drop { INTEL_FAM6_SKYLAKE_DESKTOP, 0x03, 0xc2 } from spectre_bad_microcodes? [1] https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf