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From:   Sasha Levin <Alexander.Levin@microsoft.com>
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        "stable@vger.kernel.org" <stable@vger.kernel.org>
CC:     Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
        Stephen Boyd <sboyd@codeaurora.org>,
        Sasha Levin <Alexander.Levin@microsoft.com>
Subject: [PATCH AUTOSEL for 4.4 099/115] clk: qcom: msm8916: fix mnd_width for
 codec_digcodec
Thread-Topic: [PATCH AUTOSEL for 4.4 099/115] clk: qcom: msm8916: fix
 mnd_width for codec_digcodec
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Date:   Sat, 3 Mar 2018 22:31:48 +0000
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From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

[ Upstream commit d8e488e8242ecf129eebc440c92d800a99ca109d ]

This patch fixes missing mnd_width for codec_digital clk, this is now set t=
o
8 inline with datasheet.

Fixes: 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller suppor=
t")
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
---
 drivers/clk/qcom/gcc-msm8916.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.=
c
index 2e7f03d50f4e..95a4dd290f35 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -1437,6 +1437,7 @@ static const struct freq_tbl ftbl_codec_clk[] =3D {
=20
 static struct clk_rcg2 codec_digcodec_clk_src =3D {
 	.cmd_rcgr =3D 0x1c09c,
+	.mnd_width =3D 8,
 	.hid_width =3D 5,
 	.parent_map =3D gcc_xo_gpll1_emclk_sleep_map,
 	.freq_tbl =3D ftbl_codec_clk,
--=20
2.14.1