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Miller" , Sasha Levin Subject: [PATCH AUTOSEL for 4.4 008/115] net: mvpp2: set dma mask and coherent dma mask on PPv2.2 Thread-Topic: [PATCH AUTOSEL for 4.4 008/115] net: mvpp2: set dma mask and coherent dma mask on PPv2.2 Thread-Index: AQHTsz9JFXYjUNzgzE68Vots6nha4w== Date: Sat, 3 Mar 2018 22:30:51 +0000 Message-ID: <20180303223010.27106-8-alexander.levin@microsoft.com> References: <20180303223010.27106-1-alexander.levin@microsoft.com> In-Reply-To: <20180303223010.27106-1-alexander.levin@microsoft.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [52.168.54.252] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;MW2PR2101MB1100;7:CsZRHg8XNnNopHuZ6cwpu2B8setu8yStOeT/VIO8GbLtm6eVBD65eRX+64+0UU8bXWYd+6x5FC94gCmTTJ84Gv6QUcuAakrDO0702IbQjnpJ/z9EG+wOdYBTpxTSXGCRc+5lAuUCLJgZ0Aa2ZvJef0m7WPkZc0vkwhAitovpQkuewWaZjRn+QCFAGNNINum4zYbWjq0JgUv9A4T7oO0m6/JvnQqnhZ5TV/2lx5Qd+4tf+YD2TepLRuf8cSbSfO0k x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 8b330aea-dacb-4d04-4166-08d581576874 x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(7020095)(4652020)(4534165)(4627221)(201703031133081)(201702281549075)(48565401081)(5600026)(4604075)(3008032)(2017052603307)(7193020);SRVR:MW2PR2101MB1100; x-ms-traffictypediagnostic: MW2PR2101MB1100: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Alexander.Levin@microsoft.com; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(28532068793085)(89211679590171)(58145275503218); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(8211001083)(61425038)(6040501)(2401047)(5005006)(8121501046)(10201501046)(3002001)(3231220)(944501244)(52105095)(93006095)(93001095)(6055026)(61426038)(61427038)(6041288)(20161123560045)(20161123558120)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123564045)(6072148)(201708071742011);SRVR:MW2PR2101MB1100;BCL:0;PCL:0;RULEID:;SRVR:MW2PR2101MB1100; x-forefront-prvs: 0600F93FE1 x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(39380400002)(376002)(39860400002)(396003)(366004)(346002)(199004)(189003)(22452003)(97736004)(7736002)(5250100002)(105586002)(2906002)(6506007)(72206003)(66066001)(4326008)(305945005)(10290500003)(186003)(3280700002)(102836004)(2950100002)(6666003)(2501003)(478600001)(26005)(2900100001)(10090500001)(53936002)(8676002)(25786009)(81166006)(81156014)(575784001)(54906003)(86362001)(6436002)(106356001)(110136005)(68736007)(36756003)(316002)(6512007)(5660300001)(107886003)(8936002)(1076002)(6486002)(3660700001)(99286004)(76176011)(3846002)(86612001)(14454004)(6116002)(22906009)(217873001);DIR:OUT;SFP:1102;SCL:1;SRVR:MW2PR2101MB1100;H:MW2PR2101MB1034.namprd21.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;A:1;MX:1;LANG:en; received-spf: None (protection.outlook.com: microsoft.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: ipKzXDzIbSlzQODXV0BnhapxptaSExgv0XKEV5gWSrx23Cy2MR89AqrQG7SsZJRa6lbxvEhadyqOWkAhIlUk8vQ1A8M1SdeZtqDBImNd6H0P7FeXip5JmBA3sDJGhzEQV+xkz569ludNZhNbu6w99SGQBZxC6XpNz9hOPlN1KRk= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8b330aea-dacb-4d04-4166-08d581576874 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Mar 2018 22:30:51.6977 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR2101MB1100 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Thomas Petazzoni [ Upstream commit 2067e0a13cfe0b1bdca7b91bc5e4f2740b07d478 ] On PPv2.2, the streaming mappings can be anywhere in the first 40 bits of the physical address space. However, for the coherent mappings, we still need them to be in the first 32 bits of the address space, because all BM pools share a single register to store the high 32 bits of the BM pool address, which means all BM pools must be allocated in the same 4GB memory area. Signed-off-by: Thomas Petazzoni Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/marvell/mvpp2.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/ma= rvell/mvpp2.c index ac92685dd4e5..b961860e4389 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -6448,6 +6448,20 @@ static int mvpp2_probe(struct platform_device *pdev) /* Get system's tclk rate */ priv->tclk =3D clk_get_rate(priv->pp_clk); =20 + if (priv->hw_version =3D=3D MVPP22) { + err =3D dma_set_mask(&pdev->dev, DMA_BIT_MASK(40)); + if (err) + goto err_mg_clk; + /* Sadly, the BM pools all share the same register to + * store the high 32 bits of their address. So they + * must all have the same high 32 bits, which forces + * us to restrict coherent memory to DMA_BIT_MASK(32). + */ + err =3D dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); + if (err) + goto err_mg_clk; + } + /* Initialize network controller */ err =3D mvpp2_init(pdev, priv); if (err < 0) { --=20 2.14.1