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From:   Sasha Levin <Alexander.Levin@microsoft.com>
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CC:     Geert Uytterhoeven <geert+renesas@glider.be>,
        Simon Horman <horms+renesas@verge.net.au>,
        Sasha Levin <Alexander.Levin@microsoft.com>
Subject: [PATCH AUTOSEL for 4.9 013/219] ARM: dts: r8a7794: Remove
 unit-address and reg from integrated cache
Thread-Topic: [PATCH AUTOSEL for 4.9 013/219] ARM: dts: r8a7794: Remove
 unit-address and reg from integrated cache
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Date:   Sat, 3 Mar 2018 22:28:03 +0000
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From: Geert Uytterhoeven <geert+renesas@glider.be>

[ Upstream commit 65d0b7ed40f8a3a41a0ac5ed5ca4d1874c6aaf2d ]

The Cortex-A7 cache controller is an integrated controller, and thus the
device node representing it should not have a unit-addresses or reg
property.

Fixes: 34ea4b4a827b4ee7 ("ARM: dts: r8a7794: Fix W=3D1 dtc warnings")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
---
 arch/arm/boot/dts/r8a7794.dtsi | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dts=
i
index 7e860d3737ff..6c0150dcf146 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -56,9 +56,8 @@
 			next-level-cache =3D <&L2_CA7>;
 		};
=20
-		L2_CA7: cache-controller@0 {
+		L2_CA7: cache-controller-0 {
 			compatible =3D "cache";
-			reg =3D <0>;
 			power-domains =3D <&sysc R8A7794_PD_CA7_SCU>;
 			cache-unified;
 			cache-level =3D <2>;
--=20
2.14.1