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Date:   Mon, 5 Mar 2018 10:59:26 +0000
From:   Mark Rutland <mark.rutland@arm.com>
To:     Saravana Kannan <skannan@codeaurora.org>
Cc:     robh@kernel.org, mathieu.poirier@linaro.org,
        Suzuki K Poulose <suzuki.poulose@arm.com>,
        peterz@infradead.org, sudeep.holla@arm.com, will.deacon@arm.com,
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        jonathan.cameron@huawei.com, frowand.list@gmail.com,
        leo.yan@linaro.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v11 8/8] perf: ARM DynamIQ Shared Unit PMU support
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On Fri, Mar 02, 2018 at 11:19:56AM -0800, Saravana Kannan wrote:
> On 03/02/2018 02:42 AM, Mark Rutland wrote:
> > It's important to note that the DSU PMU's event_init() ensures events
> > are affine to a single CPU, and the perf core code serializes operations
> > on those events via the context lock.
> 
> Ah, I see that now. Thanks!
> 
> > Therefore, two CPUs *won't* try to access the registers simultaneously.
> 
> Right, and this driver seems to be going through a lot of work to make sure
> all events are read in one CPU.
> 
> Do you even have an upstream target where there are multiple DSU's in a
> system? 

I have no idea, though I do beleive that it's possible for a system to
have multiple DSUs.

> If not, we can simplify a ton of this code (no hotplug notifiers, no
> migrating PMUs, no SMP calls, etc) by just adding a spinlock and letting any
> CPU read these DSU counters.

Regardless of whether we allow arbitrary CPUs to read the counters,
other logic still needs to be CPU affine, and we'll still need hotplug
notifiers and event migration.

I am not necessarily opposed to allowing read() calls from associated
CPUs, but as before, I'll leave that to Suzuki.

Thanks,
Mark.