Received: by 10.223.185.116 with SMTP id b49csp2597029wrg; Mon, 5 Mar 2018 05:47:27 -0800 (PST) X-Google-Smtp-Source: AG47ELsfN6YaNPrSVe6HYoTp+xe/K/cg8QwFObT7NB/i+bRNyBXg0Y3V0XIGsJl7Av5APpcoBo6P X-Received: by 10.98.80.15 with SMTP id e15mr15146562pfb.90.1520257647762; Mon, 05 Mar 2018 05:47:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520257647; cv=none; d=google.com; s=arc-20160816; b=f1FThPM7iwnS2uQPwHiGRt/v6nwAZp/STiB2GAEztc/auCWCgs3WAAigah/6YDbVy2 RWLieUAfs7/hMDJ7j9nclrw6o28OepKb/79/dtASL8zZ/AOqa2w0dOpoeI2WevPrxOhs LHs+1iszw8sBZMTzt4oNEIP3Ca997UZJ4H3KKaYz+WR2WkqoChVz4vj94WsPukjGM4up A1BO0wHJj/GjIvjB/pCqNCTS8DVVz9YQHn1PjmLAEMGeFym5tGeuTnhrGZ862grJ0JD5 VR62HTbkapiUkuBSY/wM8gj6k4mgIA4Tuy44UR4M2obKr0Ea7Q7Y9VtMJ7Dw1bi7s3V6 KZoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=wm/7KbzfL3VedC+gcgSIStbrpd2IKqkAYf0vdKvVexs=; b=cB4J1/Tt6/wnzGjSIi8QfjViuoLadI5kG0wMoLNpaXfyp3C5m49Z5GYYmsKtHEwisp F4liNXb2OLt4A/HqUiRa72Ws0xKTGERBjE59WGc6aCCT3ApiBWULlMnp2I7zgp4bARH4 iwBYS/k+XTUl85y6cDuBOVMG653WT/O5LE96roIOTwPxQTQGfwMrthWKN/PegIHDde/5 7iBljO5yloWhZGoC6nU5QnlSUvFo5eSx5a3HTha3V/WrNtcgUIclvwjro7Jjuc744aXh Xl9bbMhKSMm5uslOjJfGUkTa6M3y/xTwnO5UUAOTf38BtjWGfwpU9z7D5/lBfUCrLZuW ZVKw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k3si8388308pgn.791.2018.03.05.05.47.13; Mon, 05 Mar 2018 05:47:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934718AbeCELgT (ORCPT + 99 others); Mon, 5 Mar 2018 06:36:19 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:52155 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S934691AbeCELgD (ORCPT ); Mon, 5 Mar 2018 06:36:03 -0500 X-UUID: 05d880d6bcd8407b86ffb36f485389d4-20180305 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1368064596; Mon, 05 Mar 2018 19:35:59 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Mon, 5 Mar 2018 19:35:52 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Mon, 5 Mar 2018 19:35:51 +0800 From: Zhiyong Tao To: , , , CC: , , , , , , , , , , , , , Zhiyong Tao Subject: [PATCH v3 2/4] arm64: dts: mt2712: add pintcrl device node. Date: Mon, 5 Mar 2018 19:35:43 +0800 Message-ID: <1520249745-6757-3-git-send-email-zhiyong.tao@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1520249745-6757-1-git-send-email-zhiyong.tao@mediatek.com> References: <1520249745-6757-1-git-send-email-zhiyong.tao@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds pintcrl device node for mt2712. Signed-off-by: Zhiyong Tao --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index d7688bc..fb3b051 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include "mt2712-pinfunc.h" / { compatible = "mediatek,mt2712"; @@ -258,6 +259,23 @@ #clock-cells = <1>; }; + syscfg_pctl_a: syscfg_pctl_a@10005000 { + compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt2712-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + scpsys: scpsys@10006000 { compatible = "mediatek,mt2712-scpsys", "syscon"; #power-domain-cells = <1>; -- 1.9.1