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[209.85.217.176]) by smtp.gmail.com with ESMTPSA id q71sm3789511vke.37.2018.03.05.06.34.55 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Mar 2018 06:34:56 -0800 (PST) Received: by mail-ua0-f176.google.com with SMTP id k7so3116678uaa.3 for ; Mon, 05 Mar 2018 06:34:55 -0800 (PST) X-Received: by 10.176.71.234 with SMTP id w42mr10755594uac.132.1520260495234; Mon, 05 Mar 2018 06:34:55 -0800 (PST) MIME-Version: 1.0 Received: by 10.176.0.99 with HTTP; Mon, 5 Mar 2018 06:34:34 -0800 (PST) In-Reply-To: <0cd81b39-ffe9-eda3-1358-13afeb2ec25b@arm.com> References: <20180301101837.27969-1-jeffy.chen@rock-chips.com> <20180301101837.27969-14-jeffy.chen@rock-chips.com> <0cd81b39-ffe9-eda3-1358-13afeb2ec25b@arm.com> From: Tomasz Figa Date: Mon, 5 Mar 2018 23:34:34 +0900 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RESEND PATCH v6 13/14] iommu/rockchip: Add runtime PM support To: Robin Murphy Cc: Jeffy Chen , Linux Kernel Mailing List , Ricky Liang , simon xue , Heiko Stuebner , "open list:ARM/Rockchip SoC..." , Joerg Roedel , "list@263.net:IOMMU DRIVERS" , "list@263.net:IOMMU DRIVERS , Joerg Roedel ," Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 5, 2018 at 11:13 PM, Robin Murphy wrote: > On 05/03/18 13:49, Tomasz Figa wrote: > [...] >>> >>> @@ -518,7 +520,12 @@ static irqreturn_t rk_iommu_irq(int irq, void >>> *dev_id) >>> u32 int_status; >>> dma_addr_t iova; >>> irqreturn_t ret = IRQ_NONE; >>> - int i; >>> + int i, err, need_runtime_put; >> >> >> nit: need_runtime_put could be a bool. >> >>> + >>> + err = pm_runtime_get_if_in_use(iommu->dev); >>> + if (err <= 0 && err != -EINVAL) >>> + return ret; >>> + need_runtime_put = err > 0; >> >> >> Generally something must be really wrong if we end up with err == 0 >> here, because the IOMMU must be powered on to signal an interrupt. The >> only case this could happen would be if the IRQ signal was shared with >> some device from another power domain. Is it possible on Rockchip >> SoCs? If not, perhaps we should have a WARN_ON() here for such case. > > > In general, there's almost certainly some time window between the interrupt > level being latched at the GIC and the IRQ actually being taken by its > target CPU, in which potentially the power could be removed and/or the > clocks gated - especially if there are higher-priority IRQs pending at the > same time and the racing PM call is on some other CPU. Sure, it's probably > unlikely, but I wouldn't necessarily consider it completely erroneous. Clocks are not a problem here, since the handler re-enables them and clk_enable() is IRQ-safe. However, runtime PM might need sleeping, so we can't just get_sync() from the handler. I guess, we should just bail out in such case, since the power off would probably clear any internal interrupt state anyway. Also, the interrupt would be basically a page fault, during which the master device would be stalled, so it's rather unlikely that we see its driver putting the runtime PM, which would only happen after the master device resumes and competes (or something times out). So probably WARN_ON() isn't such bad idea still.